Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | |
| 18 | #include <arch/io.h> |
| 19 | #include <arch/acpi.h> |
Marshall Dawson | 8a906df | 2017-06-13 14:19:02 -0600 | [diff] [blame] | 20 | #include <bootstate.h> |
Marshall Dawson | e9b862e | 2017-09-22 15:14:46 -0600 | [diff] [blame] | 21 | #include <cpu/x86/smm.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 22 | #include <device/device.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <device/pci_ids.h> |
| 25 | #include <device/pci_ops.h> |
| 26 | #include <cbmem.h> |
Marshall Dawson | 8a906df | 2017-06-13 14:19:02 -0600 | [diff] [blame] | 27 | #include <amd_pci_util.h> |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 28 | #include <soc/southbridge.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 29 | #include <soc/smi.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 30 | #include <fchec.h> |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame^] | 31 | #include <delay.h> |
| 32 | #include <soc/pci_devs.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 33 | |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame^] | 34 | void configure_stoneyridge_uart(void) |
| 35 | { |
| 36 | u8 byte, byte2; |
| 37 | |
| 38 | if (CONFIG_UART_FOR_CONSOLE < 0 || CONFIG_UART_FOR_CONSOLE > 1) |
| 39 | return; |
| 40 | |
| 41 | /* Power on the UART and AMBA devices */ |
| 42 | byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 |
| 43 | + CONFIG_UART_FOR_CONSOLE * 2); |
| 44 | byte |= AOAC_PWR_ON_DEV; |
| 45 | write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 |
| 46 | + CONFIG_UART_FOR_CONSOLE * 2, byte); |
| 47 | |
| 48 | byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62); |
| 49 | byte |= AOAC_PWR_ON_DEV; |
| 50 | write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62, byte); |
| 51 | |
| 52 | /* Set the GPIO mux to UART */ |
| 53 | write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0); |
| 54 | write8((void *)FCH_IOMUXx8A_UART0_TXD_EGPIO138, 0); |
| 55 | write8((void *)FCH_IOMUXx8E_UART1_RTS_L_EGPIO142, 0); |
| 56 | write8((void *)FCH_IOMUXx8F_UART1_TXD_EGPIO143, 0); |
| 57 | |
| 58 | /* Wait for the UART and AMBA devices to indicate power and clock OK */ |
| 59 | do { |
| 60 | udelay(100); |
| 61 | byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG57 |
| 62 | + CONFIG_UART_FOR_CONSOLE * 2); |
| 63 | byte &= (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE); |
| 64 | byte2 = read8((void *)ACPI_MMIO_BASE + AOAC_BASE |
| 65 | + FCH_AOAC_REG63); |
| 66 | byte2 &= (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE); |
| 67 | } while (!((byte == (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE)) && |
| 68 | (byte2 == (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE)))); |
| 69 | |
| 70 | } |
| 71 | |
| 72 | void sb_pci_port80(void) |
| 73 | { |
| 74 | u8 byte; |
| 75 | |
| 76 | byte = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); |
| 77 | byte &= ~DECODE_IO_PORT_ENABLE4_H; /* disable lpc port 80 */ |
| 78 | pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); |
| 79 | } |
| 80 | |
| 81 | void sb_lpc_port80(void) |
| 82 | { |
| 83 | u8 byte; |
| 84 | |
| 85 | /* Enable LPC controller */ |
| 86 | outb(PM_LPC_GATING, PM_INDEX); |
| 87 | byte = inb(PM_DATA); |
| 88 | byte |= PM_LPC_ENABLE; |
| 89 | outb(PM_LPC_GATING, PM_INDEX); |
| 90 | outb(byte, PM_DATA); |
| 91 | |
| 92 | /* Enable port 80 LPC decode in pci function 3 configuration space. */ |
| 93 | byte = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); |
| 94 | byte |= DECODE_IO_PORT_ENABLE4_H; /* enable port 80 */ |
| 95 | pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); |
| 96 | } |
| 97 | |
| 98 | void sb_lpc_decode(void) |
| 99 | { |
| 100 | u32 tmp = 0; |
| 101 | |
| 102 | /* Enable I/O decode to LPC bus */ |
| 103 | tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2 |
| 104 | | DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0 |
| 105 | | DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2 |
| 106 | | DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4 |
| 107 | | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6 |
| 108 | | DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0 |
| 109 | | DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2 |
| 110 | | DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2 |
| 111 | | DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0 |
| 112 | | DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT |
| 113 | | DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT |
| 114 | | DECODE_ENABLE_ADLIB_PORT; |
| 115 | |
| 116 | pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, tmp); |
| 117 | } |
| 118 | |
| 119 | void sb_clk_output_48Mhz(void) |
| 120 | { |
| 121 | u32 ctrl; |
| 122 | |
| 123 | /* |
| 124 | * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so |
| 125 | * 48Mhz will be on ball AP13 (FT3b package) |
| 126 | */ |
| 127 | ctrl = read32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40)); |
| 128 | |
| 129 | /* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */ |
| 130 | ctrl &= ~FCH_MISC_REG40_OSCOUT1_EN; |
| 131 | write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl); |
| 132 | } |
| 133 | |
| 134 | static uintptr_t sb_spibase(void) |
| 135 | { |
| 136 | u32 base, enables; |
| 137 | |
| 138 | /* Make sure the base address is predictable */ |
| 139 | base = pci_read_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER); |
| 140 | enables = base & 0xf; |
| 141 | base &= ~0x3f; |
| 142 | |
| 143 | if (!base) { |
| 144 | base = SPI_BASE_ADDRESS; |
| 145 | pci_write_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER, |
| 146 | base | enables | SPI_ROM_ENABLE); |
| 147 | /* PCI_COMMAND_MEMORY is read-only and enabled. */ |
| 148 | } |
| 149 | return (uintptr_t)base; |
| 150 | } |
| 151 | |
| 152 | void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) |
| 153 | { |
| 154 | uintptr_t base = sb_spibase(); |
| 155 | write16((void *)base + SPI100_SPEED_CONFIG, |
| 156 | (norm << SPI_NORM_SPEED_NEW_SH) | |
| 157 | (fast << SPI_FAST_SPEED_NEW_SH) | |
| 158 | (alt << SPI_ALT_SPEED_NEW_SH) | |
| 159 | (tpm << SPI_TPM_SPEED_NEW_SH)); |
| 160 | write16((void *)base + SPI100_ENABLE, SPI_USE_SPI100); |
| 161 | } |
| 162 | |
| 163 | void sb_disable_4dw_burst(void) |
| 164 | { |
| 165 | uintptr_t base = sb_spibase(); |
| 166 | write16((void *)base + SPI100_HOST_PREF_CONFIG, |
| 167 | read16((void *)base + SPI100_HOST_PREF_CONFIG) |
| 168 | & ~SPI_RD4DW_EN_HOST); |
| 169 | } |
| 170 | |
| 171 | void sb_set_readspeed(u16 norm, u16 fast) |
| 172 | { |
| 173 | uintptr_t base = sb_spibase(); |
| 174 | write16((void *)base + SPI_CNTRL1, (read16((void *)base + SPI_CNTRL1) |
| 175 | & ~SPI_CNTRL1_SPEED_MASK) |
| 176 | | (norm << SPI_NORM_SPEED_SH) |
| 177 | | (fast << SPI_FAST_SPEED_SH)); |
| 178 | } |
| 179 | |
| 180 | void sb_read_mode(u32 mode) |
| 181 | { |
| 182 | uintptr_t base = sb_spibase(); |
| 183 | write32((void *)base + SPI_CNTRL0, |
| 184 | (read32((void *)base + SPI_CNTRL0) |
| 185 | & ~SPI_READ_MODE_MASK) | mode); |
| 186 | } |
| 187 | |
| 188 | void sb_tpm_decode_spi(void) |
| 189 | { |
| 190 | u32 spibase = pci_read_config32(SOC_LPC_DEV, |
| 191 | SPIROM_BASE_ADDRESS_REGISTER); |
| 192 | pci_write_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER, spibase |
| 193 | | ROUTE_TPM_2_SPI); |
| 194 | } |
| 195 | |
| 196 | /* |
| 197 | * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. |
| 198 | * |
| 199 | * Hardware should enable LPC ROM by pin straps. This function does not |
| 200 | * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. |
| 201 | * |
| 202 | * The southbridge power-on default is to map 512K ROM space. |
| 203 | * |
| 204 | */ |
| 205 | void sb_enable_rom(void) |
| 206 | { |
| 207 | u8 reg8; |
| 208 | |
| 209 | /* |
| 210 | * Decode variable LPC ROM address ranges 1 and 2. |
| 211 | * Bits 3-4 are not defined in any publicly available datasheet |
| 212 | */ |
| 213 | reg8 = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); |
| 214 | reg8 |= (1 << 3) | (1 << 4); |
| 215 | pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, reg8); |
| 216 | |
| 217 | /* |
| 218 | * LPC ROM address range 1: |
| 219 | * Enable LPC ROM range mirroring start at 0x000e(0000). |
| 220 | */ |
| 221 | pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE1_START, 0x000e); |
| 222 | |
| 223 | /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ |
| 224 | pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE1_END, 0x000f); |
| 225 | |
| 226 | /* |
| 227 | * LPC ROM address range 2: |
| 228 | * |
| 229 | * Enable LPC ROM range start at: |
| 230 | * 0xfff8(0000): 512KB |
| 231 | * 0xfff0(0000): 1MB |
| 232 | * 0xffe0(0000): 2MB |
| 233 | * 0xffc0(0000): 4MB |
| 234 | */ |
| 235 | pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE2_START, 0x10000 |
| 236 | - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); |
| 237 | |
| 238 | /* Enable LPC ROM range end at 0xffff(ffff). */ |
| 239 | pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE2_END, 0xffff); |
| 240 | } |
| 241 | |
| 242 | void bootblock_fch_early_init(void) |
| 243 | { |
| 244 | sb_enable_rom(); |
| 245 | sb_lpc_port80(); |
| 246 | sb_lpc_decode(); |
| 247 | } |
| 248 | |
| 249 | int s3_save_nvram_early(u32 dword, int size, int nvram_pos) |
| 250 | { |
| 251 | int i; |
| 252 | printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", |
| 253 | dword, size, nvram_pos); |
| 254 | |
| 255 | for (i = 0; i < size; i++) { |
| 256 | outb(nvram_pos, BIOSRAM_INDEX); |
| 257 | outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); |
| 258 | nvram_pos++; |
| 259 | } |
| 260 | |
| 261 | return nvram_pos; |
| 262 | } |
| 263 | |
| 264 | int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) |
| 265 | { |
| 266 | u32 data = *old_dword; |
| 267 | int i; |
| 268 | for (i = 0; i < size; i++) { |
| 269 | outb(nvram_pos, BIOSRAM_INDEX); |
| 270 | data &= ~(0xff << (i * 8)); |
| 271 | data |= inb(BIOSRAM_DATA) << (i * 8); |
| 272 | nvram_pos++; |
| 273 | } |
| 274 | *old_dword = data; |
| 275 | printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", |
| 276 | *old_dword, size, nvram_pos-size); |
| 277 | return nvram_pos; |
| 278 | } |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 279 | |
| 280 | int acpi_get_sleep_type(void) |
| 281 | { |
Marshall Dawson | f9592cc | 2017-11-09 16:55:31 -0700 | [diff] [blame] | 282 | return acpi_sleep_from_pm1(inw(pm_acpi_pm_cnt_blk())); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 283 | } |
| 284 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 285 | void sb_enable(device_t dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 286 | { |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 287 | printk(BIOS_DEBUG, "%s\n", __func__); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 288 | } |
| 289 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 290 | static void sb_init_acpi_ports(void) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 291 | { |
Marshall Dawson | 91b8041 | 2017-09-27 16:44:40 -0600 | [diff] [blame] | 292 | u32 reg; |
| 293 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 294 | /* We use some of these ports in SMM regardless of whether or not |
| 295 | * ACPI tables are generated. Enable these ports indiscriminately. |
| 296 | */ |
| 297 | |
| 298 | pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK); |
| 299 | pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); |
| 300 | pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); |
| 301 | pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); |
| 302 | /* CpuControl is in \_PR.CP00, 6 bytes */ |
| 303 | pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL); |
| 304 | |
| 305 | if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { |
Marshall Dawson | a05fdcb | 2017-09-27 15:01:37 -0600 | [diff] [blame] | 306 | /* APMC - SMI Command Port */ |
Marshall Dawson | e9b862e | 2017-09-22 15:14:46 -0600 | [diff] [blame] | 307 | pm_write16(PM_ACPI_SMI_CMD, APM_CNT); |
Marshall Dawson | a05fdcb | 2017-09-27 15:01:37 -0600 | [diff] [blame] | 308 | configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); |
Marshall Dawson | 91b8041 | 2017-09-27 16:44:40 -0600 | [diff] [blame] | 309 | |
| 310 | /* SMI on SlpTyp requires sending SMI before completion |
| 311 | * response of the I/O write. The BKDG also specifies |
| 312 | * clearing ForceStpClkRetry for SMI trapping. |
| 313 | */ |
| 314 | reg = pm_read32(PM_PCI_CTRL); |
| 315 | reg |= FORCE_SLPSTATE_RETRY; |
| 316 | reg &= ~FORCE_STPCLK_RETRY; |
| 317 | pm_write32(PM_PCI_CTRL, reg); |
| 318 | |
| 319 | /* Disable SlpTyp feature */ |
| 320 | reg = pm_read8(PM_RST_CTRL1); |
| 321 | reg &= ~SLPTYPE_CONTROL_EN; |
| 322 | pm_write8(PM_RST_CTRL1, reg); |
| 323 | |
| 324 | configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 325 | } else { |
| 326 | pm_write16(PM_ACPI_SMI_CMD, 0); |
| 327 | } |
| 328 | |
Marshall Dawson | 5e2e74f | 2017-11-10 09:59:56 -0700 | [diff] [blame] | 329 | /* Decode ACPI registers and enable standard features */ |
| 330 | pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD | |
| 331 | PM_ACPI_GLOBAL_EN | |
| 332 | PM_ACPI_RTC_EN_EN | |
| 333 | PM_ACPI_TIMER_EN_EN); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 334 | } |
| 335 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 336 | void southbridge_init(void *chip_info) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 337 | { |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 338 | sb_init_acpi_ports(); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 339 | } |
| 340 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 341 | void southbridge_final(void *chip_info) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 342 | { |
Richard Spiegel | 38f1940 | 2017-09-29 11:39:46 -0700 | [diff] [blame] | 343 | if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)) { |
| 344 | agesawrapper_fchecfancontrolservice(); |
| 345 | if (!IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE)) |
| 346 | enable_imc_thermal_zone(); |
| 347 | } |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 348 | } |
Marshall Dawson | 8a906df | 2017-06-13 14:19:02 -0600 | [diff] [blame] | 349 | |
| 350 | /* |
| 351 | * Update the PCI devices with a valid IRQ number |
| 352 | * that is set in the mainboard PCI_IRQ structures. |
| 353 | */ |
| 354 | static void set_pci_irqs(void *unused) |
| 355 | { |
| 356 | /* Write PCI_INTR regs 0xC00/0xC01 */ |
| 357 | write_pci_int_table(); |
| 358 | |
| 359 | /* Write IRQs for all devicetree enabled devices */ |
| 360 | write_pci_cfg_irqs(); |
| 361 | } |
| 362 | |
| 363 | /* |
| 364 | * Hook this function into the PCI state machine |
| 365 | * on entry into BS_DEV_ENABLE. |
| 366 | */ |
| 367 | BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); |