Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 4 | * Copyright (C) 2010-2017 Advanced Micro Devices, Inc. |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | |
| 18 | #include <arch/io.h> |
Marshall Dawson | 8a906df | 2017-06-13 14:19:02 -0600 | [diff] [blame] | 19 | #include <bootstate.h> |
Marshall Dawson | e9b862e | 2017-09-22 15:14:46 -0600 | [diff] [blame] | 20 | #include <cpu/x86/smm.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <device/pci_ids.h> |
| 24 | #include <device/pci_ops.h> |
| 25 | #include <cbmem.h> |
Marshall Dawson | 70f051f | 2018-03-20 10:27:41 -0600 | [diff] [blame] | 26 | #include <elog.h> |
Richard Spiegel | 2bbc3dc | 2017-12-06 16:14:58 -0700 | [diff] [blame] | 27 | #include <amdblocks/amd_pci_util.h> |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 28 | #include <soc/southbridge.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 29 | #include <soc/smi.h> |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 30 | #include <soc/amd_pci_int_defs.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 31 | #include <fchec.h> |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 32 | #include <delay.h> |
| 33 | #include <soc/pci_devs.h> |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 34 | #include <agesa_headers.h> |
| 35 | |
Richard Spiegel | 0e0e93c | 2018-03-13 10:19:51 -0700 | [diff] [blame] | 36 | /* |
| 37 | * Table of devices that need their AOAC registers enabled and waited |
| 38 | * upon (usually about .55 milliseconds). Instead of individual delays |
| 39 | * waiting for each device to become available, a single delay will be |
Richard Spiegel | 6dfbb59 | 2018-03-15 15:45:44 -0700 | [diff] [blame] | 40 | * executed. |
Richard Spiegel | 0e0e93c | 2018-03-13 10:19:51 -0700 | [diff] [blame] | 41 | */ |
| 42 | const static struct stoneyridge_aoac aoac_devs[] = { |
| 43 | { (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2), |
| 44 | (FCH_AOAC_D3_STATE_UART0 + CONFIG_UART_FOR_CONSOLE * 2) }, |
| 45 | { FCH_AOAC_D3_CONTROL_AMBA, FCH_AOAC_D3_STATE_AMBA }, |
| 46 | { FCH_AOAC_D3_CONTROL_I2C0, FCH_AOAC_D3_STATE_I2C0 }, |
| 47 | { FCH_AOAC_D3_CONTROL_I2C1, FCH_AOAC_D3_STATE_I2C1 }, |
| 48 | { FCH_AOAC_D3_CONTROL_I2C2, FCH_AOAC_D3_STATE_I2C2 }, |
| 49 | { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 } |
| 50 | }; |
| 51 | |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 52 | static int is_sata_config(void) |
| 53 | { |
| 54 | return !((CONFIG_STONEYRIDGE_SATA_MODE == SataNativeIde) |
| 55 | || (CONFIG_STONEYRIDGE_SATA_MODE == SataLegacyIde)); |
| 56 | } |
| 57 | |
Richard Spiegel | 7ea8e02 | 2018-01-16 14:40:10 -0700 | [diff] [blame] | 58 | static inline int sb_sata_enable(void) |
| 59 | { |
| 60 | /* True if IDE or AHCI. */ |
| 61 | return (CONFIG_STONEYRIDGE_SATA_MODE == SataNativeIde) || |
| 62 | (CONFIG_STONEYRIDGE_SATA_MODE == SataAhci); |
| 63 | } |
| 64 | |
| 65 | static inline int sb_ide_enable(void) |
| 66 | { |
| 67 | /* True if IDE or LEGACY IDE. */ |
| 68 | return (CONFIG_STONEYRIDGE_SATA_MODE == SataNativeIde) || |
| 69 | (CONFIG_STONEYRIDGE_SATA_MODE == SataLegacyIde); |
| 70 | } |
| 71 | |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 72 | void SetFchResetParams(FCH_RESET_INTERFACE *params) |
| 73 | { |
| 74 | params->Xhci0Enable = IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE); |
Richard Spiegel | a318d28 | 2018-01-16 13:25:40 -0700 | [diff] [blame] | 75 | params->SataEnable = sb_sata_enable(); |
| 76 | params->IdeEnable = sb_ide_enable(); |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 77 | } |
| 78 | |
| 79 | void SetFchEnvParams(FCH_INTERFACE *params) |
| 80 | { |
| 81 | params->AzaliaController = AzEnable; |
| 82 | params->SataClass = CONFIG_STONEYRIDGE_SATA_MODE; |
| 83 | params->SataEnable = is_sata_config(); |
| 84 | params->IdeEnable = !params->SataEnable; |
| 85 | params->SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == SataLegacyIde); |
| 86 | } |
| 87 | |
| 88 | void SetFchMidParams(FCH_INTERFACE *params) |
| 89 | { |
| 90 | SetFchEnvParams(params); |
| 91 | } |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 92 | |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 93 | /* |
| 94 | * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 95 | * provides a visible association with the index, therefore helping |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 96 | * maintainability of table. If a new index/name is defined in |
| 97 | * amd_pci_int_defs.h, just add the pair at the end of this table. |
| 98 | * Order is not important. |
| 99 | */ |
| 100 | const static struct irq_idx_name irq_association[] = { |
Richard Spiegel | e89d444 | 2017-12-08 07:52:42 -0700 | [diff] [blame] | 101 | { PIRQ_A, "INTA#" }, |
| 102 | { PIRQ_B, "INTB#" }, |
| 103 | { PIRQ_C, "INTC#" }, |
| 104 | { PIRQ_D, "INTD#" }, |
| 105 | { PIRQ_E, "INTE#" }, |
| 106 | { PIRQ_F, "INTF#" }, |
| 107 | { PIRQ_G, "INTG#" }, |
| 108 | { PIRQ_H, "INTH#" }, |
| 109 | { PIRQ_MISC, "Misc" }, |
| 110 | { PIRQ_MISC0, "Misc0" }, |
| 111 | { PIRQ_MISC1, "Misc1" }, |
| 112 | { PIRQ_MISC2, "Misc2" }, |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 113 | { PIRQ_SIRQA, "Ser IRQ INTA" }, |
| 114 | { PIRQ_SIRQB, "Ser IRQ INTB" }, |
| 115 | { PIRQ_SIRQC, "Ser IRQ INTC" }, |
| 116 | { PIRQ_SIRQD, "Ser IRQ INTD" }, |
Richard Spiegel | e89d444 | 2017-12-08 07:52:42 -0700 | [diff] [blame] | 117 | { PIRQ_SCI, "SCI" }, |
| 118 | { PIRQ_SMBUS, "SMBUS" }, |
| 119 | { PIRQ_ASF, "ASF" }, |
| 120 | { PIRQ_HDA, "HDA" }, |
| 121 | { PIRQ_FC, "FC" }, |
| 122 | { PIRQ_PMON, "PerMon" }, |
| 123 | { PIRQ_SD, "SD" }, |
| 124 | { PIRQ_SDIO, "SDIOt" }, |
| 125 | { PIRQ_IMC0, "IMC INT0" }, |
| 126 | { PIRQ_IMC1, "IMC INT1" }, |
| 127 | { PIRQ_IMC2, "IMC INT2" }, |
| 128 | { PIRQ_IMC3, "IMC INT3" }, |
| 129 | { PIRQ_IMC4, "IMC INT4" }, |
| 130 | { PIRQ_IMC5, "IMC INT5" }, |
| 131 | { PIRQ_EHCI, "EHCI" }, |
| 132 | { PIRQ_XHCI, "XHCI" }, |
| 133 | { PIRQ_SATA, "SATA" }, |
| 134 | { PIRQ_GPIO, "GPIO" }, |
| 135 | { PIRQ_I2C0, "I2C0" }, |
| 136 | { PIRQ_I2C1, "I2C1" }, |
| 137 | { PIRQ_I2C2, "I2C2" }, |
| 138 | { PIRQ_I2C3, "I2C3" }, |
| 139 | { PIRQ_UART0, "UART0" }, |
| 140 | { PIRQ_UART1, "UART1" }, |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 141 | }; |
| 142 | |
Richard Spiegel | ebf3aa8 | 2017-11-24 07:47:42 -0700 | [diff] [blame] | 143 | /* |
| 144 | * Structure to simplify code obtaining the total of used wide IO |
| 145 | * registers and the size assigned to each. |
| 146 | */ |
| 147 | static struct wide_io_ioport_and_bits { |
| 148 | uint32_t enable; |
| 149 | uint16_t port; |
| 150 | uint8_t alt; |
| 151 | } wio_io_en[TOTAL_WIDEIO_PORTS] = { |
| 152 | { |
| 153 | LPC_WIDEIO0_ENABLE, |
| 154 | LPC_WIDEIO_GENERIC_PORT, |
| 155 | LPC_ALT_WIDEIO0_ENABLE |
| 156 | }, |
| 157 | { |
| 158 | LPC_WIDEIO1_ENABLE, |
| 159 | LPC_WIDEIO1_GENERIC_PORT, |
| 160 | LPC_ALT_WIDEIO1_ENABLE |
| 161 | }, |
| 162 | { |
| 163 | LPC_WIDEIO2_ENABLE, |
| 164 | LPC_WIDEIO2_GENERIC_PORT, |
| 165 | LPC_ALT_WIDEIO2_ENABLE |
| 166 | } |
| 167 | }; |
| 168 | |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 169 | const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) |
| 170 | { |
| 171 | *size = ARRAY_SIZE(irq_association); |
| 172 | return irq_association; |
| 173 | } |
| 174 | |
Richard Spiegel | 6fcb9b0 | 2018-04-18 08:06:33 -0700 | [diff] [blame] | 175 | void sb_program_gpios(const struct soc_amd_gpio *gpio_ptr, size_t size) |
Richard Spiegel | e539c85 | 2017-12-25 18:25:58 -0700 | [diff] [blame] | 176 | { |
| 177 | void *tmp_ptr; |
Richard Spiegel | e539c85 | 2017-12-25 18:25:58 -0700 | [diff] [blame] | 178 | uint8_t control, mux, index; |
| 179 | |
Richard Spiegel | e539c85 | 2017-12-25 18:25:58 -0700 | [diff] [blame] | 180 | for (index = 0; index < size; index++) { |
| 181 | mux = gpio_ptr[index].function; |
| 182 | control = gpio_ptr[index].control; |
| 183 | tmp_ptr = (void *)(gpio_ptr[index].gpio + AMD_GPIO_MUX); |
| 184 | write8(tmp_ptr, mux & AMD_GPIO_MUX_MASK); |
| 185 | |
| 186 | /* |
| 187 | * Get the address of AMD_GPIO_CONTROL (dword) relative |
| 188 | * to the desired pin and program bits 16-23. |
| 189 | */ |
| 190 | tmp_ptr = (void *)(gpio_ptr[index].gpio * sizeof(uint32_t) + |
| 191 | AMD_GPIO_CONTROL + 2); |
| 192 | write8(tmp_ptr, control); |
| 193 | } |
Richard Spiegel | e539c85 | 2017-12-25 18:25:58 -0700 | [diff] [blame] | 194 | } |
| 195 | |
Richard Spiegel | ebf3aa8 | 2017-11-24 07:47:42 -0700 | [diff] [blame] | 196 | /** |
| 197 | * @brief Find the size of a particular wide IO |
| 198 | * |
| 199 | * @param index = index of desired wide IO |
| 200 | * |
| 201 | * @return size of desired wide IO |
| 202 | */ |
| 203 | uint16_t sb_wideio_size(int index) |
| 204 | { |
| 205 | uint32_t enable_register; |
| 206 | uint16_t size = 0; |
| 207 | uint8_t alternate_register; |
| 208 | |
| 209 | if (index >= TOTAL_WIDEIO_PORTS) |
| 210 | return size; |
| 211 | enable_register = pci_read_config32(SOC_LPC_DEV, |
| 212 | LPC_IO_OR_MEM_DECODE_ENABLE); |
| 213 | alternate_register = pci_read_config8(SOC_LPC_DEV, |
| 214 | LPC_ALT_WIDEIO_RANGE_ENABLE); |
| 215 | if (enable_register & wio_io_en[index].enable) |
| 216 | size = (alternate_register & wio_io_en[index].alt) ? |
| 217 | 16 : 512; |
| 218 | return size; |
| 219 | } |
| 220 | |
| 221 | /** |
| 222 | * @brief Identify if any LPC wide IO is covering the IO range |
| 223 | * |
| 224 | * @param start = start of IO range |
| 225 | * @param size = size of IO range |
| 226 | * |
| 227 | * @return Index of wide IO covering the range or error |
| 228 | */ |
| 229 | int sb_find_wideio_range(uint16_t start, uint16_t size) |
| 230 | { |
| 231 | uint32_t enable_register; |
| 232 | int i, index = WIDEIO_RANGE_ERROR; |
| 233 | uint16_t end, current_size, start_wideio, end_wideio; |
| 234 | |
| 235 | end = start + size; |
| 236 | enable_register = pci_read_config32(SOC_LPC_DEV, |
| 237 | LPC_IO_OR_MEM_DECODE_ENABLE); |
| 238 | for (i = 0; i < TOTAL_WIDEIO_PORTS; i++) { |
| 239 | current_size = sb_wideio_size(i); |
| 240 | if (current_size == 0) |
| 241 | continue; |
| 242 | start_wideio = pci_read_config16(SOC_LPC_DEV, |
| 243 | wio_io_en[i].port); |
| 244 | end_wideio = start_wideio + current_size; |
| 245 | if ((start >= start_wideio) && (end <= end_wideio)) { |
| 246 | index = i; |
| 247 | break; |
| 248 | } |
| 249 | } |
| 250 | return index; |
| 251 | } |
| 252 | |
| 253 | /** |
| 254 | * @brief Program a LPC wide IO to support an IO range |
| 255 | * |
| 256 | * @param start = start of range to be routed through wide IO |
| 257 | * @param size = size of range to be routed through wide IO |
| 258 | * |
| 259 | * @return Index of wide IO register used or error |
| 260 | */ |
| 261 | int sb_set_wideio_range(uint16_t start, uint16_t size) |
| 262 | { |
| 263 | int i, index = WIDEIO_RANGE_ERROR; |
| 264 | uint32_t enable_register; |
| 265 | uint8_t alternate_register; |
| 266 | |
| 267 | enable_register = pci_read_config32(SOC_LPC_DEV, |
| 268 | LPC_IO_OR_MEM_DECODE_ENABLE); |
| 269 | alternate_register = pci_read_config8(SOC_LPC_DEV, |
| 270 | LPC_ALT_WIDEIO_RANGE_ENABLE); |
| 271 | for (i = 0; i < TOTAL_WIDEIO_PORTS; i++) { |
| 272 | if (enable_register & wio_io_en[i].enable) |
| 273 | continue; |
| 274 | index = i; |
| 275 | pci_write_config16(SOC_LPC_DEV, wio_io_en[i].port, start); |
| 276 | enable_register |= wio_io_en[i].enable; |
| 277 | pci_write_config32(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, |
| 278 | enable_register); |
| 279 | if (size <= 16) |
| 280 | alternate_register |= wio_io_en[i].alt; |
| 281 | else |
| 282 | alternate_register &= ~wio_io_en[i].alt; |
| 283 | pci_write_config8(SOC_LPC_DEV, |
| 284 | LPC_ALT_WIDEIO_RANGE_ENABLE, |
| 285 | alternate_register); |
| 286 | break; |
| 287 | } |
| 288 | return index; |
| 289 | } |
| 290 | |
Garrett Kirkendall | a0ff6fc | 2018-03-06 09:23:47 -0600 | [diff] [blame] | 291 | static void power_on_aoac_device(int aoac_device_control_register) |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 292 | { |
Garrett Kirkendall | a0ff6fc | 2018-03-06 09:23:47 -0600 | [diff] [blame] | 293 | uint8_t byte; |
| 294 | uint8_t *register_pointer = (uint8_t *)(uintptr_t)AOAC_MMIO_BASE |
| 295 | + aoac_device_control_register; |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 296 | |
| 297 | /* Power on the UART and AMBA devices */ |
Garrett Kirkendall | a0ff6fc | 2018-03-06 09:23:47 -0600 | [diff] [blame] | 298 | byte = read8(register_pointer); |
| 299 | byte |= FCH_AOAC_PWR_ON_DEV; |
| 300 | write8(register_pointer, byte); |
| 301 | } |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 302 | |
Garrett Kirkendall | a0ff6fc | 2018-03-06 09:23:47 -0600 | [diff] [blame] | 303 | static bool is_aoac_device_enabled(int aoac_device_status_register) |
| 304 | { |
| 305 | uint8_t byte; |
| 306 | byte = read8((uint8_t *)(uintptr_t)AOAC_MMIO_BASE |
| 307 | + aoac_device_status_register); |
| 308 | byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE); |
| 309 | if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE)) |
| 310 | return true; |
| 311 | else |
| 312 | return false; |
| 313 | } |
| 314 | |
Richard Spiegel | 0e0e93c | 2018-03-13 10:19:51 -0700 | [diff] [blame] | 315 | void enable_aoac_devices(void) |
Garrett Kirkendall | a0ff6fc | 2018-03-06 09:23:47 -0600 | [diff] [blame] | 316 | { |
| 317 | bool status; |
Richard Spiegel | 0e0e93c | 2018-03-13 10:19:51 -0700 | [diff] [blame] | 318 | int i; |
Garrett Kirkendall | a0ff6fc | 2018-03-06 09:23:47 -0600 | [diff] [blame] | 319 | |
Richard Spiegel | 0e0e93c | 2018-03-13 10:19:51 -0700 | [diff] [blame] | 320 | for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) |
| 321 | power_on_aoac_device(aoac_devs[i].enable); |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 322 | |
Richard Spiegel | 0e0e93c | 2018-03-13 10:19:51 -0700 | [diff] [blame] | 323 | /* Wait for AOAC devices to indicate power and clock OK */ |
| 324 | do { |
| 325 | udelay(100); |
| 326 | status = true; |
| 327 | for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) |
| 328 | status &= is_aoac_device_enabled(aoac_devs[i].status); |
| 329 | } while (!status); |
| 330 | } |
| 331 | |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 332 | void sb_pci_port80(void) |
| 333 | { |
| 334 | u8 byte; |
| 335 | |
| 336 | byte = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); |
| 337 | byte &= ~DECODE_IO_PORT_ENABLE4_H; /* disable lpc port 80 */ |
| 338 | pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); |
| 339 | } |
| 340 | |
| 341 | void sb_lpc_port80(void) |
| 342 | { |
| 343 | u8 byte; |
| 344 | |
| 345 | /* Enable LPC controller */ |
| 346 | outb(PM_LPC_GATING, PM_INDEX); |
| 347 | byte = inb(PM_DATA); |
| 348 | byte |= PM_LPC_ENABLE; |
| 349 | outb(PM_LPC_GATING, PM_INDEX); |
| 350 | outb(byte, PM_DATA); |
| 351 | |
| 352 | /* Enable port 80 LPC decode in pci function 3 configuration space. */ |
| 353 | byte = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); |
| 354 | byte |= DECODE_IO_PORT_ENABLE4_H; /* enable port 80 */ |
| 355 | pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); |
| 356 | } |
| 357 | |
| 358 | void sb_lpc_decode(void) |
| 359 | { |
| 360 | u32 tmp = 0; |
| 361 | |
| 362 | /* Enable I/O decode to LPC bus */ |
| 363 | tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2 |
| 364 | | DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0 |
| 365 | | DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2 |
| 366 | | DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4 |
| 367 | | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6 |
| 368 | | DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0 |
| 369 | | DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2 |
| 370 | | DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2 |
| 371 | | DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0 |
| 372 | | DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT |
| 373 | | DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT |
| 374 | | DECODE_ENABLE_ADLIB_PORT; |
| 375 | |
| 376 | pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, tmp); |
| 377 | } |
| 378 | |
Garrett Kirkendall | 9858bd2 | 2018-03-07 15:38:14 -0600 | [diff] [blame] | 379 | void sb_acpi_mmio_decode(void) |
| 380 | { |
| 381 | uint8_t byte; |
| 382 | |
| 383 | /* Enable ACPI MMIO range 0xfed80000 - 0xfed81fff */ |
| 384 | outb(PM_ISA_CONTROL, PM_INDEX); |
| 385 | byte = inb(PM_DATA); |
| 386 | byte |= MMIO_EN; |
| 387 | outb(PM_ISA_CONTROL, PM_INDEX); |
| 388 | outb(byte, PM_DATA); |
| 389 | } |
| 390 | |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 391 | void sb_clk_output_48Mhz(void) |
| 392 | { |
| 393 | u32 ctrl; |
Garrett Kirkendall | d255830 | 2018-03-06 09:05:20 -0600 | [diff] [blame] | 394 | u32 *misc_clk_cntl_1_ptr = (u32 *)(uintptr_t)(MISC_MMIO_BASE |
| 395 | + MISC_MISC_CLK_CNTL_1); |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 396 | |
| 397 | /* |
| 398 | * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so |
| 399 | * 48Mhz will be on ball AP13 (FT3b package) |
| 400 | */ |
Garrett Kirkendall | d255830 | 2018-03-06 09:05:20 -0600 | [diff] [blame] | 401 | ctrl = read32(misc_clk_cntl_1_ptr); |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 402 | |
| 403 | /* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */ |
Garrett Kirkendall | d255830 | 2018-03-06 09:05:20 -0600 | [diff] [blame] | 404 | ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB; |
| 405 | write32(misc_clk_cntl_1_ptr, ctrl); |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 406 | } |
| 407 | |
| 408 | static uintptr_t sb_spibase(void) |
| 409 | { |
| 410 | u32 base, enables; |
| 411 | |
| 412 | /* Make sure the base address is predictable */ |
| 413 | base = pci_read_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER); |
| 414 | enables = base & 0xf; |
| 415 | base &= ~0x3f; |
| 416 | |
| 417 | if (!base) { |
| 418 | base = SPI_BASE_ADDRESS; |
| 419 | pci_write_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER, |
| 420 | base | enables | SPI_ROM_ENABLE); |
| 421 | /* PCI_COMMAND_MEMORY is read-only and enabled. */ |
| 422 | } |
| 423 | return (uintptr_t)base; |
| 424 | } |
| 425 | |
| 426 | void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) |
| 427 | { |
| 428 | uintptr_t base = sb_spibase(); |
| 429 | write16((void *)base + SPI100_SPEED_CONFIG, |
| 430 | (norm << SPI_NORM_SPEED_NEW_SH) | |
| 431 | (fast << SPI_FAST_SPEED_NEW_SH) | |
| 432 | (alt << SPI_ALT_SPEED_NEW_SH) | |
| 433 | (tpm << SPI_TPM_SPEED_NEW_SH)); |
| 434 | write16((void *)base + SPI100_ENABLE, SPI_USE_SPI100); |
| 435 | } |
| 436 | |
| 437 | void sb_disable_4dw_burst(void) |
| 438 | { |
| 439 | uintptr_t base = sb_spibase(); |
| 440 | write16((void *)base + SPI100_HOST_PREF_CONFIG, |
| 441 | read16((void *)base + SPI100_HOST_PREF_CONFIG) |
| 442 | & ~SPI_RD4DW_EN_HOST); |
| 443 | } |
| 444 | |
| 445 | void sb_set_readspeed(u16 norm, u16 fast) |
| 446 | { |
| 447 | uintptr_t base = sb_spibase(); |
| 448 | write16((void *)base + SPI_CNTRL1, (read16((void *)base + SPI_CNTRL1) |
| 449 | & ~SPI_CNTRL1_SPEED_MASK) |
| 450 | | (norm << SPI_NORM_SPEED_SH) |
| 451 | | (fast << SPI_FAST_SPEED_SH)); |
| 452 | } |
| 453 | |
| 454 | void sb_read_mode(u32 mode) |
| 455 | { |
| 456 | uintptr_t base = sb_spibase(); |
| 457 | write32((void *)base + SPI_CNTRL0, |
| 458 | (read32((void *)base + SPI_CNTRL0) |
| 459 | & ~SPI_READ_MODE_MASK) | mode); |
| 460 | } |
| 461 | |
Garrett Kirkendall | 6575306 | 2018-03-07 16:12:11 -0600 | [diff] [blame] | 462 | /* |
| 463 | * Enable FCH to decode TPM associated Memory and IO regions |
| 464 | * |
| 465 | * Enable decoding of TPM cycles defined in TPM 1.2 spec |
| 466 | * Enable decoding of legacy TPM addresses: IO addresses 0x7f- |
| 467 | * 0x7e and 0xef-0xee. |
| 468 | * This function should be called if TPM is connected in any way to the FCH and |
| 469 | * conforms to the regions decoded. |
| 470 | * Absent any other routing configuration the TPM cycles will be claimed by the |
| 471 | * LPC bus |
| 472 | */ |
| 473 | void sb_tpm_decode(void) |
| 474 | { |
| 475 | u32 value; |
| 476 | |
| 477 | value = pci_read_config32(SOC_LPC_DEV, LPC_TRUSTED_PLATFORM_MODULE); |
| 478 | value |= TPM_12_EN | TPM_LEGACY_EN; |
| 479 | pci_write_config32(SOC_LPC_DEV, LPC_TRUSTED_PLATFORM_MODULE, value); |
| 480 | } |
| 481 | |
| 482 | /* |
| 483 | * Enable FCH to decode TPM associated Memory and IO regions to SPI |
| 484 | * |
| 485 | * This should be used if TPM is connected to SPI bus. |
| 486 | * Assumes SPI address space is already configured via a call to sb_spibase(). |
| 487 | */ |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 488 | void sb_tpm_decode_spi(void) |
| 489 | { |
Garrett Kirkendall | 6575306 | 2018-03-07 16:12:11 -0600 | [diff] [blame] | 490 | /* Enable TPM decoding to FCH */ |
| 491 | sb_tpm_decode(); |
| 492 | |
| 493 | /* Route TPM accesses to SPI */ |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 494 | u32 spibase = pci_read_config32(SOC_LPC_DEV, |
| 495 | SPIROM_BASE_ADDRESS_REGISTER); |
| 496 | pci_write_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER, spibase |
| 497 | | ROUTE_TPM_2_SPI); |
| 498 | } |
| 499 | |
| 500 | /* |
| 501 | * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. |
| 502 | * |
| 503 | * Hardware should enable LPC ROM by pin straps. This function does not |
| 504 | * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. |
| 505 | * |
| 506 | * The southbridge power-on default is to map 512K ROM space. |
| 507 | * |
| 508 | */ |
| 509 | void sb_enable_rom(void) |
| 510 | { |
| 511 | u8 reg8; |
| 512 | |
| 513 | /* |
| 514 | * Decode variable LPC ROM address ranges 1 and 2. |
| 515 | * Bits 3-4 are not defined in any publicly available datasheet |
| 516 | */ |
| 517 | reg8 = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); |
| 518 | reg8 |= (1 << 3) | (1 << 4); |
| 519 | pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, reg8); |
| 520 | |
| 521 | /* |
| 522 | * LPC ROM address range 1: |
| 523 | * Enable LPC ROM range mirroring start at 0x000e(0000). |
| 524 | */ |
| 525 | pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE1_START, 0x000e); |
| 526 | |
| 527 | /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ |
| 528 | pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE1_END, 0x000f); |
| 529 | |
| 530 | /* |
| 531 | * LPC ROM address range 2: |
| 532 | * |
| 533 | * Enable LPC ROM range start at: |
| 534 | * 0xfff8(0000): 512KB |
| 535 | * 0xfff0(0000): 1MB |
| 536 | * 0xffe0(0000): 2MB |
| 537 | * 0xffc0(0000): 4MB |
| 538 | */ |
| 539 | pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE2_START, 0x10000 |
| 540 | - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); |
| 541 | |
| 542 | /* Enable LPC ROM range end at 0xffff(ffff). */ |
| 543 | pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE2_END, 0xffff); |
| 544 | } |
| 545 | |
Marc Jones | cfb1680 | 2018-04-20 16:27:41 -0600 | [diff] [blame^] | 546 | static void sb_lpc_early_setup(void) |
| 547 | { |
| 548 | uint32_t dword; |
| 549 | |
| 550 | /* Enable SPI prefetch */ |
| 551 | dword = pci_read_config32(SOC_LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL); |
| 552 | dword |= SPI_FROM_HOST_PREFETCH_EN | SPI_FROM_USB_PREFETCH_EN; |
| 553 | pci_write_config32(SOC_LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL, dword); |
| 554 | |
| 555 | if (IS_ENABLED(CONFIG_STONEYRIDGE_LEGACY_FREE)) { |
| 556 | /* Decode SIOs at 2E/2F and 4E/4F */ |
| 557 | dword = pci_read_config32(SOC_LPC_DEV, |
| 558 | LPC_IO_OR_MEM_DECODE_ENABLE); |
| 559 | dword |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE; |
| 560 | pci_write_config32(SOC_LPC_DEV, |
| 561 | LPC_IO_OR_MEM_DECODE_ENABLE, dword); |
| 562 | } |
| 563 | } |
| 564 | |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 565 | void bootblock_fch_early_init(void) |
| 566 | { |
| 567 | sb_enable_rom(); |
| 568 | sb_lpc_port80(); |
| 569 | sb_lpc_decode(); |
Marc Jones | cfb1680 | 2018-04-20 16:27:41 -0600 | [diff] [blame^] | 570 | sb_lpc_early_setup(); |
Garrett Kirkendall | 64294eb | 2018-03-16 13:00:46 -0500 | [diff] [blame] | 571 | sb_spibase(); |
Marc Jones | cfb1680 | 2018-04-20 16:27:41 -0600 | [diff] [blame^] | 572 | sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ |
Garrett Kirkendall | e7513e0d | 2018-03-14 12:01:36 -0500 | [diff] [blame] | 573 | sb_acpi_mmio_decode(); |
Richard Spiegel | 0e0e93c | 2018-03-13 10:19:51 -0700 | [diff] [blame] | 574 | enable_aoac_devices(); |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 575 | } |
| 576 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 577 | void sb_enable(device_t dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 578 | { |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 579 | printk(BIOS_DEBUG, "%s\n", __func__); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 580 | } |
| 581 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 582 | static void sb_init_acpi_ports(void) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 583 | { |
Marshall Dawson | 91b8041 | 2017-09-27 16:44:40 -0600 | [diff] [blame] | 584 | u32 reg; |
| 585 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 586 | /* We use some of these ports in SMM regardless of whether or not |
| 587 | * ACPI tables are generated. Enable these ports indiscriminately. |
| 588 | */ |
| 589 | |
| 590 | pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK); |
| 591 | pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); |
| 592 | pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); |
| 593 | pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); |
| 594 | /* CpuControl is in \_PR.CP00, 6 bytes */ |
| 595 | pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL); |
| 596 | |
| 597 | if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { |
Marshall Dawson | a05fdcb | 2017-09-27 15:01:37 -0600 | [diff] [blame] | 598 | /* APMC - SMI Command Port */ |
Marshall Dawson | e9b862e | 2017-09-22 15:14:46 -0600 | [diff] [blame] | 599 | pm_write16(PM_ACPI_SMI_CMD, APM_CNT); |
Marshall Dawson | a05fdcb | 2017-09-27 15:01:37 -0600 | [diff] [blame] | 600 | configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); |
Marshall Dawson | 91b8041 | 2017-09-27 16:44:40 -0600 | [diff] [blame] | 601 | |
| 602 | /* SMI on SlpTyp requires sending SMI before completion |
| 603 | * response of the I/O write. The BKDG also specifies |
| 604 | * clearing ForceStpClkRetry for SMI trapping. |
| 605 | */ |
| 606 | reg = pm_read32(PM_PCI_CTRL); |
| 607 | reg |= FORCE_SLPSTATE_RETRY; |
| 608 | reg &= ~FORCE_STPCLK_RETRY; |
| 609 | pm_write32(PM_PCI_CTRL, reg); |
| 610 | |
| 611 | /* Disable SlpTyp feature */ |
| 612 | reg = pm_read8(PM_RST_CTRL1); |
| 613 | reg &= ~SLPTYPE_CONTROL_EN; |
| 614 | pm_write8(PM_RST_CTRL1, reg); |
| 615 | |
| 616 | configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 617 | } else { |
| 618 | pm_write16(PM_ACPI_SMI_CMD, 0); |
| 619 | } |
| 620 | |
Marshall Dawson | 5e2e74f | 2017-11-10 09:59:56 -0700 | [diff] [blame] | 621 | /* Decode ACPI registers and enable standard features */ |
| 622 | pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD | |
| 623 | PM_ACPI_GLOBAL_EN | |
| 624 | PM_ACPI_RTC_EN_EN | |
| 625 | PM_ACPI_TIMER_EN_EN); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 626 | } |
| 627 | |
Marshall Dawson | 70f051f | 2018-03-20 10:27:41 -0600 | [diff] [blame] | 628 | static void print_num_status_bits(int num_bits, uint32_t status, |
| 629 | const char *const bit_names[]) |
| 630 | { |
| 631 | int i; |
| 632 | |
| 633 | if (!status) |
| 634 | return; |
| 635 | |
| 636 | for (i = num_bits - 1; i >= 0; i--) { |
| 637 | if (status & (1 << i)) { |
| 638 | if (bit_names[i]) |
| 639 | printk(BIOS_DEBUG, "%s ", bit_names[i]); |
| 640 | else |
| 641 | printk(BIOS_DEBUG, "BIT%d ", i); |
| 642 | } |
| 643 | } |
| 644 | } |
| 645 | |
| 646 | static uint16_t reset_pm1_status(void) |
| 647 | { |
| 648 | uint16_t pm1_sts = inw(ACPI_PM_EVT_BLK); |
| 649 | outw(pm1_sts, ACPI_PM_EVT_BLK); |
| 650 | return pm1_sts; |
| 651 | } |
| 652 | |
| 653 | static uint16_t print_pm1_status(uint16_t pm1_sts) |
| 654 | { |
| 655 | static const char *const pm1_sts_bits[] = { |
| 656 | [0] = "TMROF", |
| 657 | [4] = "BMSTATUS", |
| 658 | [5] = "GBL", |
| 659 | [8] = "PWRBTN", |
| 660 | [10] = "RTC", |
| 661 | [14] = "PCIEXPWAK", |
| 662 | [15] = "WAK", |
| 663 | }; |
| 664 | |
| 665 | if (!pm1_sts) |
| 666 | return 0; |
| 667 | |
| 668 | printk(BIOS_SPEW, "PM1_STS: "); |
| 669 | print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits); |
| 670 | printk(BIOS_SPEW, "\n"); |
| 671 | |
| 672 | return pm1_sts; |
| 673 | } |
| 674 | |
| 675 | static void sb_log_pm1_status(uint16_t pm1_sts) |
| 676 | { |
| 677 | if (!IS_ENABLED(CONFIG_ELOG)) |
| 678 | return; |
| 679 | |
| 680 | if (pm1_sts & PWRBTN_STS) |
| 681 | elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); |
| 682 | |
| 683 | if (pm1_sts & RTC_STS) |
| 684 | elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); |
| 685 | |
| 686 | if (pm1_sts & PCIEXPWAK_STS) |
| 687 | elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); |
| 688 | } |
| 689 | |
| 690 | static void sb_clear_pm1_status(void) |
| 691 | { |
| 692 | uint16_t pm1_sts = reset_pm1_status(); |
| 693 | sb_log_pm1_status(pm1_sts); |
| 694 | print_pm1_status(pm1_sts); |
| 695 | } |
| 696 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 697 | void southbridge_init(void *chip_info) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 698 | { |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 699 | sb_init_acpi_ports(); |
Marshall Dawson | 70f051f | 2018-03-20 10:27:41 -0600 | [diff] [blame] | 700 | sb_clear_pm1_status(); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 701 | } |
| 702 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 703 | void southbridge_final(void *chip_info) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 704 | { |
Richard Spiegel | 6a38914 | 2018-03-05 14:28:10 -0700 | [diff] [blame] | 705 | uint8_t restored_power = PM_S5_AT_POWER_RECOVERY; |
| 706 | |
Richard Spiegel | 38f1940 | 2017-09-29 11:39:46 -0700 | [diff] [blame] | 707 | if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)) { |
| 708 | agesawrapper_fchecfancontrolservice(); |
| 709 | if (!IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE)) |
| 710 | enable_imc_thermal_zone(); |
| 711 | } |
Richard Spiegel | 6a38914 | 2018-03-05 14:28:10 -0700 | [diff] [blame] | 712 | if (IS_ENABLED(CONFIG_MAINBOARD_POWER_RESTORE)) |
| 713 | restored_power = PM_RESTORE_S0_IF_PREV_S0; |
| 714 | pm_write8(PM_RTC_SHADOW, restored_power); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 715 | } |
Marshall Dawson | 8a906df | 2017-06-13 14:19:02 -0600 | [diff] [blame] | 716 | |
| 717 | /* |
| 718 | * Update the PCI devices with a valid IRQ number |
| 719 | * that is set in the mainboard PCI_IRQ structures. |
| 720 | */ |
| 721 | static void set_pci_irqs(void *unused) |
| 722 | { |
| 723 | /* Write PCI_INTR regs 0xC00/0xC01 */ |
| 724 | write_pci_int_table(); |
| 725 | |
| 726 | /* Write IRQs for all devicetree enabled devices */ |
| 727 | write_pci_cfg_irqs(); |
| 728 | } |
| 729 | |
| 730 | /* |
| 731 | * Hook this function into the PCI state machine |
| 732 | * on entry into BS_DEV_ENABLE. |
| 733 | */ |
| 734 | BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); |