Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
Nico Huber | 55c5777 | 2018-12-16 03:39:35 +0100 | [diff] [blame] | 3 | register "gpu_pp_up_delay_ms" = "200" |
| 4 | register "gpu_pp_down_delay_ms" = " 50" |
| 5 | register "gpu_pp_cycle_delay_ms" = "500" |
| 6 | register "gpu_pp_backlight_on_delay_ms" = " 1" |
| 7 | register "gpu_pp_backlight_off_delay_ms" = "200" |
| 8 | |
| 9 | register "gpu_pch_backlight_pwm_hz" = "200" |
| 10 | |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 11 | # Deep Sx states |
Duncan Laurie | 1fe32d6 | 2017-04-10 21:02:13 -0700 | [diff] [blame] | 12 | register "deep_s3_enable_ac" = "0" |
| 13 | register "deep_s3_enable_dc" = "0" |
| 14 | register "deep_s5_enable_ac" = "1" |
| 15 | register "deep_s5_enable_dc" = "1" |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 16 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" |
| 17 | |
Matt DeVillier | 89393d6 | 2019-01-05 02:16:39 -0600 | [diff] [blame] | 18 | register "eist_enable" = "1" |
| 19 | |
Shelley Chen | da6e4f6 | 2017-06-29 16:13:33 -0700 | [diff] [blame] | 20 | # Mapping of USB port # to device |
| 21 | #+----------------+-------+-----------------------------------+ |
| 22 | #| Device | Port# | Rev | |
| 23 | #+----------------+-------+-----------------------------------+ |
| 24 | #| USB C | 1 | 2/3 | |
| 25 | #| USB A Rear | 2 | 2/3 | |
| 26 | #| USB A Front | 3 | 2/3 | |
| 27 | #| USB A Front | 4 | 2/3 | |
| 28 | #| USB A Rear | 5 | 2 on base celeron, 2/3 all others | |
| 29 | #| USB A Rear | 6 | 2 on base celeron, 2/3 all others | |
| 30 | #| Bluetooth | 7 | | |
| 31 | #| Daughter Board | 8 | | |
| 32 | #+----------------+-------+-----------------------------------+ |
| 33 | |
| 34 | # Bitmap for Wake Enable on USB attach/detach |
| 35 | register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) | \ |
| 36 | USB_PORT_WAKE_ENABLE(3) | \ |
| 37 | USB_PORT_WAKE_ENABLE(4) | \ |
| 38 | USB_PORT_WAKE_ENABLE(5) | \ |
| 39 | USB_PORT_WAKE_ENABLE(6)" |
| 40 | register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) | \ |
| 41 | USB_PORT_WAKE_ENABLE(3) | \ |
| 42 | USB_PORT_WAKE_ENABLE(4) | \ |
| 43 | USB_PORT_WAKE_ENABLE(5) | \ |
| 44 | USB_PORT_WAKE_ENABLE(6)" |
| 45 | |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 46 | # GPE configuration |
| 47 | # Note that GPE events called out in ASL code rely on this |
| 48 | # route. i.e. If this route changes then the affected GPE |
| 49 | # offset bits also need to be changed. |
| 50 | register "gpe0_dw0" = "GPP_B" |
| 51 | register "gpe0_dw1" = "GPP_D" |
| 52 | register "gpe0_dw2" = "GPP_E" |
| 53 | |
| 54 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 55 | register "gen1_dec" = "0x00fc0801" |
| 56 | register "gen2_dec" = "0x000c0201" |
| 57 | # EC memory map range is 0x900-0x9ff |
| 58 | register "gen3_dec" = "0x00fc0901" |
| 59 | |
Tsai, Gaggery | b2a3ac4 | 2017-08-22 10:55:13 +0800 | [diff] [blame] | 60 | # Enable DPTF |
| 61 | register "dptf_enable" = "1" |
| 62 | |
Shelley Chen | 6dd9e59 | 2017-12-20 10:43:25 -0800 | [diff] [blame] | 63 | # Enable S0ix |
| 64 | register "s0ix_enable" = "1" |
| 65 | |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 66 | # FSP Configuration |
| 67 | register "ProbelessTrace" = "0" |
Kevin Chiu | a63f4c4 | 2018-01-08 09:54:08 +0800 | [diff] [blame] | 68 | register "SataSalpSupport" = "0" |
Kane Chen | 91ea9f0 | 2017-12-13 11:35:54 +0800 | [diff] [blame] | 69 | register "SataMode" = "0" |
David Wu | 0f82905 | 2017-12-11 14:08:11 +0800 | [diff] [blame] | 70 | register "SataPortsEnable[0]" = "1" |
Shelley Chen | e8365aa | 2017-04-24 13:11:43 -0700 | [diff] [blame] | 71 | register "SataPortsEnable[1]" = "1" |
Gaggery Tsai | bc37c67 | 2017-09-29 13:40:04 +0800 | [diff] [blame] | 72 | register "SataPortsDevSlp[1]" = "1" |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 73 | register "DspEnable" = "1" |
| 74 | register "IoBufferOwnership" = "3" |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 75 | register "SsicPortEnable" = "0" |
Shelley Chen | c516883 | 2017-03-21 15:04:04 -0700 | [diff] [blame] | 76 | register "ScsEmmcHs400Enabled" = "0" |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 77 | register "PttSwitch" = "0" |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 78 | register "SkipExtGfxScan" = "1" |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 79 | register "HeciEnabled" = "0" |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 80 | register "SaGv" = "3" |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 81 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 82 | register "PmConfigSlpS4MinAssert" = "1" # 1s |
| 83 | register "PmConfigSlpSusMinAssert" = "1" # 500ms |
| 84 | register "PmConfigSlpAMinAssert" = "3" # 2s |
| 85 | register "PmTimerDisabled" = "1" |
| 86 | register "SendVrMbxCmd" = "1" # IMVP8 workaround |
| 87 | |
Rizwan Qureshi | bbff157 | 2017-12-07 02:10:06 +0530 | [diff] [blame] | 88 | # Intersil VR c-state issue workaround |
| 89 | # send VR mailbox command for IA/GT/SA rails |
| 90 | register "IslVrCmd" = "2" |
| 91 | |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 92 | # VR Settings Configuration for 4 Domains |
| 93 | #+----------------+-------+-------+-------+-------+ |
| 94 | #| Domain/Setting | SA | IA | GTUS | GTS | |
| 95 | #+----------------+-------+-------+-------+-------+ |
| 96 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 97 | #| Psi2Threshold | 4A | 5A | 5A | 5A | |
| 98 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 99 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 100 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 101 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 102 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 103 | #| IccMax | 7A | 34A | 35A | 35A | |
| 104 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
Gaggery Tsai | 63278ab | 2018-01-22 11:17:28 +0800 | [diff] [blame] | 105 | #| AcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m | |
| 106 | #| DcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m | |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 107 | #+----------------+-------+-------+-------+-------+ |
Gaggery Tsai | 2ce9090 | 2018-01-15 22:48:18 +0800 | [diff] [blame] | 108 | #Note: IccMax settings are moved to SoC code |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 109 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 110 | .vr_config_enable = 1, |
| 111 | .psi1threshold = VR_CFG_AMP(20), |
| 112 | .psi2threshold = VR_CFG_AMP(4), |
| 113 | .psi3threshold = VR_CFG_AMP(1), |
| 114 | .psi3enable = 1, |
| 115 | .psi4enable = 1, |
| 116 | .imon_slope = 0x0, |
| 117 | .imon_offset = 0x0, |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 118 | .voltage_limit = 1520, |
Gaggery Tsai | 63278ab | 2018-01-22 11:17:28 +0800 | [diff] [blame] | 119 | .ac_loadline = 1030, |
| 120 | .dc_loadline = 1030, |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 121 | }" |
| 122 | |
| 123 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 124 | .vr_config_enable = 1, |
| 125 | .psi1threshold = VR_CFG_AMP(20), |
| 126 | .psi2threshold = VR_CFG_AMP(5), |
| 127 | .psi3threshold = VR_CFG_AMP(1), |
| 128 | .psi3enable = 1, |
| 129 | .psi4enable = 1, |
| 130 | .imon_slope = 0x0, |
| 131 | .imon_offset = 0x0, |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 132 | .voltage_limit = 1520, |
Gaggery Tsai | 63278ab | 2018-01-22 11:17:28 +0800 | [diff] [blame] | 133 | .ac_loadline = 240, |
| 134 | .dc_loadline = 240, |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 135 | }" |
| 136 | |
| 137 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 138 | .vr_config_enable = 1, |
| 139 | .psi1threshold = VR_CFG_AMP(20), |
| 140 | .psi2threshold = VR_CFG_AMP(5), |
| 141 | .psi3threshold = VR_CFG_AMP(1), |
| 142 | .psi3enable = 1, |
| 143 | .psi4enable = 1, |
| 144 | .imon_slope = 0x0, |
| 145 | .imon_offset = 0x0, |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 146 | .voltage_limit = 1520, |
Gaggery Tsai | 63278ab | 2018-01-22 11:17:28 +0800 | [diff] [blame] | 147 | .ac_loadline = 310, |
| 148 | .dc_loadline = 310, |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 149 | }" |
| 150 | |
| 151 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 152 | .vr_config_enable = 1, |
| 153 | .psi1threshold = VR_CFG_AMP(20), |
| 154 | .psi2threshold = VR_CFG_AMP(5), |
| 155 | .psi3threshold = VR_CFG_AMP(1), |
| 156 | .psi3enable = 1, |
| 157 | .psi4enable = 1, |
| 158 | .imon_slope = 0x0, |
| 159 | .imon_offset = 0x0, |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 160 | .voltage_limit = 1520, |
Gaggery Tsai | 63278ab | 2018-01-22 11:17:28 +0800 | [diff] [blame] | 161 | .ac_loadline = 310, |
| 162 | .dc_loadline = 310, |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 163 | }" |
| 164 | |
Naresh G Solanki | 561f7fc | 2017-04-20 16:45:01 +0530 | [diff] [blame] | 165 | # Enable Root port 3(x1) for LAN. |
| 166 | register "PcieRpEnable[2]" = "1" |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 167 | # Enable CLKREQ# |
Naresh G Solanki | 561f7fc | 2017-04-20 16:45:01 +0530 | [diff] [blame] | 168 | register "PcieRpClkReqSupport[2]" = "1" |
| 169 | # RP 3 uses SRCCLKREQ0# |
| 170 | register "PcieRpClkReqNumber[2]" = "0" |
Kane Chen | 6708d3a | 2017-10-11 12:39:46 +0800 | [diff] [blame] | 171 | # RP 3, Enable Advanced Error Reporting |
| 172 | register "PcieRpAdvancedErrorReporting[2]" = "1" |
| 173 | # RP 3, Enable Latency Tolerance Reporting Mechanism |
| 174 | register "PcieRpLtrEnable[2]" = "1" |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 175 | # RP 3 uses uses CLK SRC 0 |
| 176 | register "PcieRpClkSrcNumber[2]" = "0" |
Naresh G Solanki | 561f7fc | 2017-04-20 16:45:01 +0530 | [diff] [blame] | 177 | |
| 178 | # Enable Root port 4(x1) for WLAN. |
| 179 | register "PcieRpEnable[3]" = "1" |
| 180 | # Enable CLKREQ# |
| 181 | register "PcieRpClkReqSupport[3]" = "1" |
| 182 | # RP 4 uses SRCCLKREQ5# |
| 183 | register "PcieRpClkReqNumber[3]" = "5" |
Kane Chen | 6708d3a | 2017-10-11 12:39:46 +0800 | [diff] [blame] | 184 | # RP 4, Enable Advanced Error Reporting |
| 185 | register "PcieRpAdvancedErrorReporting[3]" = "1" |
| 186 | # RP 4, Enable Latency Tolerance Reporting Mechanism |
| 187 | register "PcieRpLtrEnable[3]" = "1" |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 188 | # RP 4 uses uses CLK SRC 5 |
| 189 | register "PcieRpClkSrcNumber[3]" = "5" |
Naresh G Solanki | 561f7fc | 2017-04-20 16:45:01 +0530 | [diff] [blame] | 190 | |
| 191 | # Enable Root port 5(x4) for NVMe. |
| 192 | register "PcieRpEnable[4]" = "1" |
| 193 | # Enable CLKREQ# |
| 194 | register "PcieRpClkReqSupport[4]" = "1" |
| 195 | # RP 5 uses SRCCLKREQ1# |
| 196 | register "PcieRpClkReqNumber[4]" = "1" |
Kane Chen | 6708d3a | 2017-10-11 12:39:46 +0800 | [diff] [blame] | 197 | # RP 5, Enable Advanced Error Reporting |
| 198 | register "PcieRpAdvancedErrorReporting[4]" = "1" |
| 199 | # RP 5, Enable Latency Tolerance Reporting Mechanism |
| 200 | register "PcieRpLtrEnable[4]" = "1" |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 201 | # RP 5 uses CLK SRC 1 |
| 202 | register "PcieRpClkSrcNumber[4]" = "1" |
Naresh G Solanki | 561f7fc | 2017-04-20 16:45:01 +0530 | [diff] [blame] | 203 | |
| 204 | # Enable Root port 9 for BtoB. |
| 205 | register "PcieRpEnable[8]" = "1" |
| 206 | # Enable CLKREQ# |
| 207 | register "PcieRpClkReqSupport[8]" = "1" |
| 208 | # RP 9 uses SRCCLKREQ2# |
| 209 | register "PcieRpClkReqNumber[8]" = "2" |
Kane Chen | 6708d3a | 2017-10-11 12:39:46 +0800 | [diff] [blame] | 210 | # RP 9, Enable Advanced Error Reporting |
| 211 | register "PcieRpAdvancedErrorReporting[8]" = "1" |
| 212 | # RP 9, Enable Latency Tolerance Reporting Mechanism |
| 213 | register "PcieRpLtrEnable[8]" = "1" |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 214 | # RP 9 uses uses CLK SRC 2 |
| 215 | register "PcieRpClkSrcNumber[8]" = "2" |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 216 | |
Zhongze Hu | 12f656c | 2018-02-16 00:53:02 -0800 | [diff] [blame] | 217 | # Enable Root port 11 for BtoB. |
| 218 | register "PcieRpEnable[10]" = "1" |
| 219 | # Enable CLKREQ# |
| 220 | register "PcieRpClkReqSupport[10]" = "1" |
| 221 | # RP 11 uses SRCCLKREQ2# |
| 222 | register "PcieRpClkReqNumber[10]" = "2" |
| 223 | # RP 11, Enable Advanced Error Reporting |
| 224 | register "PcieRpAdvancedErrorReporting[10]" = "1" |
| 225 | # RP 11, Enable Latency Tolerance Reporting Mechanism |
| 226 | register "PcieRpLtrEnable[10]" = "1" |
| 227 | # RP 11 uses uses CLK SRC 2 |
| 228 | register "PcieRpClkSrcNumber[10]" = "2" |
| 229 | |
| 230 | # Enable Root port 12 for BtoB. |
| 231 | register "PcieRpEnable[11]" = "1" |
| 232 | # Enable CLKREQ# |
| 233 | register "PcieRpClkReqSupport[11]" = "1" |
| 234 | # RP 12 uses SRCCLKREQ2# |
| 235 | register "PcieRpClkReqNumber[11]" = "2" |
| 236 | # RP 12, Enable Advanced Error Reporting |
| 237 | register "PcieRpAdvancedErrorReporting[11]" = "1" |
| 238 | # RP 12, Enable Latency Tolerance Reporting Mechanism |
| 239 | register "PcieRpLtrEnable[11]" = "1" |
| 240 | # RP 12 uses uses CLK SRC 2 |
| 241 | register "PcieRpClkSrcNumber[11]" = "2" |
| 242 | |
Shelley Chen | c516883 | 2017-03-21 15:04:04 -0700 | [diff] [blame] | 243 | register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C |
| 244 | register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-A Rear |
| 245 | register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Front |
| 246 | register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A Front |
| 247 | register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # Type-A Rear |
| 248 | register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Rear |
| 249 | register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth |
| 250 | register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A 2.0 / Debug |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 251 | |
Shelley Chen | c516883 | 2017-03-21 15:04:04 -0700 | [diff] [blame] | 252 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C |
| 253 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear |
| 254 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front |
| 255 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front |
Naresh G Solanki | 561f7fc | 2017-04-20 16:45:01 +0530 | [diff] [blame] | 256 | register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear |
| 257 | register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 258 | |
Shelley Chen | c516883 | 2017-03-21 15:04:04 -0700 | [diff] [blame] | 259 | register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # HDMI CEC |
| 260 | register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM |
| 261 | register "i2c_voltage[2]" = "I2C_VOLTAGE_3V3" # Debug |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 262 | register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio |
| 263 | |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 264 | # Intel Common SoC Config |
| 265 | #+-------------------+---------------------------+ |
| 266 | #| Field | Value | |
| 267 | #+-------------------+---------------------------+ |
| 268 | #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | |
| 269 | #| GSPI0 | cr50 TPM. Early init is | |
| 270 | #| | required to set up a BAR | |
| 271 | #| | for TPM communication | |
| 272 | #| | before memory is up | |
| 273 | #| I2C5 | Audio | |
| 274 | #+-------------------+---------------------------+ |
Shelley Chen | 5aa64b9 | 2017-06-09 13:05:29 -0700 | [diff] [blame] | 275 | |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 276 | register "common_soc_config" = "{ |
| 277 | .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
| 278 | .gspi[0] = { |
| 279 | .speed_mhz = 1, |
| 280 | .early_init = 1, |
| 281 | }, |
| 282 | .i2c[5] = { |
Shelley Chen | 8bd8cd3 | 2018-01-22 10:26:31 -0800 | [diff] [blame] | 283 | .speed = I2C_SPEED_FAST, |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 284 | .speed_config[0] = { |
| 285 | .speed = I2C_SPEED_FAST, |
| 286 | .scl_lcnt = 194, |
| 287 | .scl_hcnt = 100, |
| 288 | .sda_hold = 36, |
| 289 | }, |
Shelley Chen | 8bd8cd3 | 2018-01-22 10:26:31 -0800 | [diff] [blame] | 290 | }, |
| 291 | }" |
| 292 | |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 293 | # Must leave UART0 enabled or SD/eMMC will not work as PCI |
| 294 | register "SerialIoDevMode" = "{ |
Zhongze Hu | 1fa724b | 2018-03-16 17:11:07 -0700 | [diff] [blame] | 295 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
Shelley Chen | 5537f02 | 2017-11-22 16:55:27 -0800 | [diff] [blame] | 296 | [PchSerialIoIndexI2C1] = PchSerialIoDisabled, |
Zhongze Hu | 1fa724b | 2018-03-16 17:11:07 -0700 | [diff] [blame] | 297 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
Shelley Chen | c516883 | 2017-03-21 15:04:04 -0700 | [diff] [blame] | 298 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
| 299 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 300 | [PchSerialIoIndexI2C5] = PchSerialIoPci, |
| 301 | [PchSerialIoIndexSpi0] = PchSerialIoPci, |
Shelley Chen | c516883 | 2017-03-21 15:04:04 -0700 | [diff] [blame] | 302 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, |
Duncan Laurie | 3879ef4 | 2018-03-02 14:39:47 -0800 | [diff] [blame] | 303 | [PchSerialIoIndexUart0] = PchSerialIoSkipInit, |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 304 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, |
| 305 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, |
| 306 | }" |
| 307 | |
| 308 | register "speed_shift_enable" = "1" |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 309 | register "power_limits_config" = "{ |
| 310 | .tdp_psyspl2 = 90, |
| 311 | .psys_pmax = 120, |
| 312 | }" |
Kevin Chiu | 09f8a83 | 2018-01-08 11:50:59 +0800 | [diff] [blame] | 313 | register "tcc_offset" = "6" # TCC of 94C |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 314 | |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 315 | device cpu_cluster 0 on |
| 316 | device lapic 0 on end |
| 317 | end |
| 318 | device domain 0 on |
| 319 | device pci 00.0 on end # Host Bridge |
| 320 | device pci 02.0 on end # Integrated Graphics Device |
Felix Singer | 9c1c009 | 2020-07-29 20:48:08 +0200 | [diff] [blame] | 321 | device pci 04.0 on end # SA thermal subsystem |
Emil Lundmark | 2ad7ea0 | 2018-05-22 19:32:35 +0200 | [diff] [blame] | 322 | device pci 14.0 on |
| 323 | chip drivers/usb/acpi |
| 324 | register "desc" = ""Root Hub"" |
| 325 | register "type" = "UPC_TYPE_HUB" |
| 326 | device usb 0.0 on |
| 327 | chip drivers/usb/acpi |
| 328 | register "desc" = ""USB2 Type-C Rear"" |
| 329 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 330 | device usb 2.0 on end |
| 331 | end |
| 332 | chip drivers/usb/acpi |
| 333 | register "desc" = ""USB2 Type-A Rear Left"" |
| 334 | register "type" = "UPC_TYPE_A" |
| 335 | device usb 2.1 on end |
| 336 | end |
| 337 | chip drivers/usb/acpi |
Emil Lundmark | 2ad7ea0 | 2018-05-22 19:32:35 +0200 | [diff] [blame] | 338 | register "desc" = ""USB2 Type-A Rear Right"" |
| 339 | register "type" = "UPC_TYPE_A" |
| 340 | device usb 2.4 on end |
| 341 | end |
| 342 | chip drivers/usb/acpi |
| 343 | register "desc" = ""USB2 Type-A Rear Middle"" |
| 344 | register "type" = "UPC_TYPE_A" |
| 345 | device usb 2.5 on end |
| 346 | end |
| 347 | chip drivers/usb/acpi |
| 348 | register "desc" = ""USB2 Bluetooth"" |
| 349 | register "type" = "UPC_TYPE_INTERNAL" |
| 350 | device usb 2.6 on end |
| 351 | end |
| 352 | chip drivers/usb/acpi |
| 353 | register "desc" = ""USB3 Type-C Rear"" |
| 354 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 355 | device usb 3.0 on end |
| 356 | end |
| 357 | chip drivers/usb/acpi |
| 358 | register "desc" = ""USB3 Type-A Rear Left"" |
| 359 | register "type" = "UPC_TYPE_USB3_A" |
| 360 | device usb 3.1 on end |
| 361 | end |
| 362 | chip drivers/usb/acpi |
Emil Lundmark | 2ad7ea0 | 2018-05-22 19:32:35 +0200 | [diff] [blame] | 363 | register "desc" = ""USB3 Type-A Rear Right"" |
| 364 | register "type" = "UPC_TYPE_USB3_A" |
| 365 | device usb 3.4 on end |
| 366 | end |
| 367 | chip drivers/usb/acpi |
| 368 | register "desc" = ""USB3 Type-A Rear Middle"" |
| 369 | register "type" = "UPC_TYPE_USB3_A" |
| 370 | device usb 3.5 on end |
| 371 | end |
| 372 | end |
| 373 | end |
| 374 | end # USB xHCI |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 375 | device pci 14.1 off end # USB xDCI (OTG) |
| 376 | device pci 14.2 on end # Thermal Subsystem |
Felix Singer | e218667 | 2020-07-29 23:20:52 +0200 | [diff] [blame] | 377 | device pci 14.3 off end # Camera |
Zhongze Hu | 1fa724b | 2018-03-16 17:11:07 -0700 | [diff] [blame] | 378 | device pci 15.0 on end # I2C #0 |
Shelley Chen | 5537f02 | 2017-11-22 16:55:27 -0800 | [diff] [blame] | 379 | device pci 15.1 off end # I2C #1 |
Zhongze Hu | 1fa724b | 2018-03-16 17:11:07 -0700 | [diff] [blame] | 380 | device pci 15.2 on end # I2C #2 |
Shelley Chen | 5537f02 | 2017-11-22 16:55:27 -0800 | [diff] [blame] | 381 | device pci 15.3 off end # I2C #3 |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 382 | device pci 16.0 on end # Management Engine Interface 1 |
| 383 | device pci 16.1 off end # Management Engine Interface 2 |
| 384 | device pci 16.2 off end # Management Engine IDE-R |
| 385 | device pci 16.3 off end # Management Engine KT Redirection |
| 386 | device pci 16.4 off end # Management Engine Interface 3 |
Shelley Chen | c516883 | 2017-03-21 15:04:04 -0700 | [diff] [blame] | 387 | device pci 17.0 on end # SATA |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 388 | device pci 19.0 on end # UART #2 |
Furquan Shaikh | b87ad06 | 2018-10-23 08:03:06 -0700 | [diff] [blame] | 389 | device pci 19.1 on end # I2C #5 |
Shelley Chen | c516883 | 2017-03-21 15:04:04 -0700 | [diff] [blame] | 390 | device pci 19.2 off end # I2C #4 |
Matt DeVillier | f061a73 | 2018-06-11 01:19:45 -0500 | [diff] [blame] | 391 | device pci 1c.0 on end # PCI Express Port 1 |
| 392 | device pci 1c.1 off end # PCI Express Port 2 |
| 393 | # PCI Express Port 3 for LAN, will be swapped to port 1 by FSP |
| 394 | device pci 1c.2 on |
Gaggery Tsai | 2ecf3f8 | 2017-11-02 09:58:06 +0800 | [diff] [blame] | 395 | chip drivers/net |
Gaggery Tsai | d7de7bc | 2017-12-20 13:12:57 +0800 | [diff] [blame] | 396 | register "customized_leds" = "0x0fa5" |
Gaggery Tsai | 61c817d | 2017-11-23 13:23:57 +0800 | [diff] [blame] | 397 | register "wake" = "GPE0_PCI_EXP" |
Gaggery Tsai | 2ecf3f8 | 2017-11-02 09:58:06 +0800 | [diff] [blame] | 398 | device pci 00.0 on end |
Edward O'Callaghan | 0e13806 | 2020-03-23 13:06:42 +1100 | [diff] [blame] | 399 | register "device_index" = "0" |
Gaggery Tsai | 2ecf3f8 | 2017-11-02 09:58:06 +0800 | [diff] [blame] | 400 | end |
Matt DeVillier | f061a73 | 2018-06-11 01:19:45 -0500 | [diff] [blame] | 401 | end # PCI Express Port 3 |
Naresh G Solanki | 561f7fc | 2017-04-20 16:45:01 +0530 | [diff] [blame] | 402 | device pci 1c.3 on |
Furquan Shaikh | a266d1e | 2020-10-04 12:52:54 -0700 | [diff] [blame^] | 403 | chip drivers/wifi/generic |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 404 | register "wake" = "GPE0_PCI_EXP" |
| 405 | device pci 00.0 on end |
| 406 | end |
Naresh G Solanki | 561f7fc | 2017-04-20 16:45:01 +0530 | [diff] [blame] | 407 | end # PCI Express Port 4 for WLAN |
| 408 | device pci 1c.4 on end # PCI Express Port 5 for NVMe |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 409 | device pci 1c.5 off end # PCI Express Port 6 |
| 410 | device pci 1c.6 off end # PCI Express Port 7 |
| 411 | device pci 1c.7 off end # PCI Express Port 8 |
David Wu | 5f7fa72 | 2017-12-11 14:40:36 +0800 | [diff] [blame] | 412 | device pci 1d.0 on # PCI Express Port 9 for 2nd LAN |
| 413 | chip drivers/net |
Gaggery Tsai | d7de7bc | 2017-12-20 13:12:57 +0800 | [diff] [blame] | 414 | register "customized_leds" = "0x0fa5" |
Edward O'Callaghan | 0e13806 | 2020-03-23 13:06:42 +1100 | [diff] [blame] | 415 | register "device_index" = "1" |
David Wu | 5f7fa72 | 2017-12-11 14:40:36 +0800 | [diff] [blame] | 416 | device pci 00.0 on end |
| 417 | end |
| 418 | end # PCI Express Port 9 for BtoB |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 419 | device pci 1d.1 off end # PCI Express Port 10 |
Zhongze Hu | 12f656c | 2018-02-16 00:53:02 -0800 | [diff] [blame] | 420 | device pci 1d.2 on end # PCI Express Port 11 |
| 421 | device pci 1d.3 on end # PCI Express Port 12 |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 422 | device pci 1e.0 on end # UART #0 |
| 423 | device pci 1e.1 off end # UART #1 |
Shelley Chen | 5aa64b9 | 2017-06-09 13:05:29 -0700 | [diff] [blame] | 424 | device pci 1e.2 on |
| 425 | chip drivers/spi/acpi |
| 426 | register "hid" = "ACPI_DT_NAMESPACE_HID" |
| 427 | register "compat_string" = ""google,cr50"" |
| 428 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" |
| 429 | device spi 0 on end |
| 430 | end |
| 431 | end # GSPI #0 |
Shelley Chen | c516883 | 2017-03-21 15:04:04 -0700 | [diff] [blame] | 432 | device pci 1e.3 off end # GSPI #1 |
| 433 | device pci 1e.4 off end # eMMC |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 434 | device pci 1e.5 off end # SDIO |
| 435 | device pci 1e.6 on end # SDCard |
| 436 | device pci 1f.0 on |
| 437 | chip ec/google/chromeec |
| 438 | device pnp 0c09.0 on end |
| 439 | end |
| 440 | end # LPC Interface |
| 441 | device pci 1f.1 on end # P2SB |
| 442 | device pci 1f.2 on end # Power Management Controller |
| 443 | device pci 1f.3 on end # Intel HDA |
| 444 | device pci 1f.4 on end # SMBus |
| 445 | device pci 1f.5 on end # PCH SPI |
| 446 | device pci 1f.6 off end # GbE |
| 447 | end |
| 448 | end |