commit 09f8a834b3a57bb35021c0f1705a2583135edb7e
author Kevin Chiu <Kevin.Chiu@quantatw.com> Mon Jan 08 11:50:59 2018 +0800
committer Martin Roth <martinroth@google.com> Fri Jan 12 18:19:00 2018 +0000
tree 57467f136eca6ce1ce08ed202438d6d5a8d28d69
parent e13a269f589b0ede64c24bb8cf7644a92d05792a

mb/google/fizz: update DPTF settings

TCPU:
  _CRT: 100
  _PSV: 93
  _TRT: 100/5(s)
TSR0:
  _CRT: 83
  _PSV: 70
  _TRT: 100/10(s)
TSR1:
  _CRT: 73
  _PSV: 67
  _TRT: 100/30(s)

TCC: 6 for 94'C

PL1:
  max: 15W
  min: 3W

BUG=b:70294260
BRANCH=master
TEST=build
Change-Id: Ie17f4395d2199009fd68a600d818f2be54bc8935
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/23155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/mainboard/google/fizz/devicetree.cb

diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index a3ae44c..0af7603 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -267,7 +267,7 @@
 
 	register "speed_shift_enable" = "1"
 	register "tdp_psyspl2" = "90"
-	register "tcc_offset" = "10"     # TCC of 90C
+	register "tcc_offset" = "6"     # TCC of 94C
 
 	# Use default SD card detect GPIO configuration
 	register "sdcard_cd_gpio_default" = "GPP_A7"