mb/google/fizz: Enable PCIe port 11, 12
Our CFM daughter card would like to use individual PCIe lanes for two
different devices on the card.
dlaurie@ has reconfigured PCIe port 9-12 from 1x4 to 1x2 + 2x1 on b2b
connector on fizz to meet the requirement:
https://chrome-internal-review.googlesource.com/571936
We also need to enable the ports on device tree.
BUG=b:72523836
TEST=none
BRANCH=fizz
Change-Id: Icded9850d833752680e0174b6c476e657817b319
Reviewed-on: https://chromium-review.googlesource.com/923867
Commit-Ready: Zhongze Hu <frankhu@google.com>
Tested-by: Zhongze Hu <frankhu@google.com>
Reviewed-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/924860
Commit-Queue: Shelley Chen <shchen@chromium.org>
Tested-by: Shelley Chen <shchen@chromium.org>
Signed-off-by: Zhongze Hu <frankhu@chromium.org>
Reviewed-on: https://review.coreboot.org/23845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index 3b084ff..5eeb03c 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -228,6 +228,32 @@
# RP 9 uses uses CLK SRC 2
register "PcieRpClkSrcNumber[8]" = "2"
+ # Enable Root port 11 for BtoB.
+ register "PcieRpEnable[10]" = "1"
+ # Enable CLKREQ#
+ register "PcieRpClkReqSupport[10]" = "1"
+ # RP 11 uses SRCCLKREQ2#
+ register "PcieRpClkReqNumber[10]" = "2"
+ # RP 11, Enable Advanced Error Reporting
+ register "PcieRpAdvancedErrorReporting[10]" = "1"
+ # RP 11, Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpLtrEnable[10]" = "1"
+ # RP 11 uses uses CLK SRC 2
+ register "PcieRpClkSrcNumber[10]" = "2"
+
+ # Enable Root port 12 for BtoB.
+ register "PcieRpEnable[11]" = "1"
+ # Enable CLKREQ#
+ register "PcieRpClkReqSupport[11]" = "1"
+ # RP 12 uses SRCCLKREQ2#
+ register "PcieRpClkReqNumber[11]" = "2"
+ # RP 12, Enable Advanced Error Reporting
+ register "PcieRpAdvancedErrorReporting[11]" = "1"
+ # RP 12, Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpLtrEnable[11]" = "1"
+ # RP 12 uses uses CLK SRC 2
+ register "PcieRpClkSrcNumber[11]" = "2"
+
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C
register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-A Rear
register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Front
@@ -351,8 +377,8 @@
end
end # PCI Express Port 9 for BtoB
device pci 1d.1 off end # PCI Express Port 10
- device pci 1d.2 off end # PCI Express Port 11
- device pci 1d.3 off end # PCI Express Port 12
+ device pci 1d.2 on end # PCI Express Port 11
+ device pci 1d.3 on end # PCI Express Port 12
device pci 1e.0 on end # UART #0
device pci 1e.1 off end # UART #1
device pci 1e.2 on