commit 6708d3abc744d3d51472ef0028f9a7ad96fd8f11
author Kane Chen <kane.chen@intel.com> Wed Oct 11 12:39:46 2017 +0800
committer Martin Roth <martinroth@google.com> Mon Oct 16 00:20:07 2017 +0000
tree 7b5ea32e2477bdd9ae4bbc30d6085804eb1dca5b
parent ec1a24ca02221daeef521ccc8d934a7e0abb7ae5

mb/google/fizz: enable AER for PCIe root ports

Enable PCIe Advanced Error Reporting for PCIe
root port 2, 3, 4 ,8.

BUG=b:64798078
TEST="lspci" shows that AER is enabled in the capabilities list.

Change-Id: I6438250d674e7d06cdecd8f25fadebca1973721e
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/21946
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/mainboard/google/fizz/devicetree.cb

diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index ad934c3..1590252 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -166,6 +166,10 @@
 	register "PcieRpClkReqSupport[2]" = "1"
 	# RP 3 uses SRCCLKREQ0#
 	register "PcieRpClkReqNumber[2]" = "0"
+	# RP 3, Enable Advanced Error Reporting
+	register "PcieRpAdvancedErrorReporting[2]" = "1"
+	# RP 3, Enable Latency Tolerance Reporting Mechanism
+	register "PcieRpLtrEnable[2]" = "1"
 
 	# Enable Root port 4(x1) for WLAN.
 	register "PcieRpEnable[3]" = "1"
@@ -173,6 +177,10 @@
 	register "PcieRpClkReqSupport[3]" = "1"
 	# RP 4 uses SRCCLKREQ5#
 	register "PcieRpClkReqNumber[3]" = "5"
+	# RP 4, Enable Advanced Error Reporting
+	register "PcieRpAdvancedErrorReporting[3]" = "1"
+	# RP 4, Enable Latency Tolerance Reporting Mechanism
+	register "PcieRpLtrEnable[3]" = "1"
 
 	# Enable Root port 5(x4) for NVMe.
 	register "PcieRpEnable[4]" = "1"
@@ -180,6 +188,10 @@
 	register "PcieRpClkReqSupport[4]" = "1"
 	# RP 5 uses SRCCLKREQ1#
 	register "PcieRpClkReqNumber[4]" = "1"
+	# RP 5, Enable Advanced Error Reporting
+	register "PcieRpAdvancedErrorReporting[4]" = "1"
+	# RP 5, Enable Latency Tolerance Reporting Mechanism
+	register "PcieRpLtrEnable[4]" = "1"
 
 	# Enable Root port 9 for BtoB.
 	register "PcieRpEnable[8]" = "1"
@@ -187,6 +199,10 @@
 	register "PcieRpClkReqSupport[8]" = "1"
 	# RP 9 uses SRCCLKREQ2#
 	register "PcieRpClkReqNumber[8]" = "2"
+	# RP 9, Enable Advanced Error Reporting
+	register "PcieRpAdvancedErrorReporting[8]" = "1"
+	# RP 9, Enable Latency Tolerance Reporting Mechanism
+	register "PcieRpLtrEnable[8]" = "1"
 
 	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C
 	register "usb2_ports[1]" = "USB2_PORT_MID(OC3)"		# Type-A Rear