skylake: update processor power limits configuration
Update processor power limit configuration parameters based on
common code base support for Intel Skylake SoC based platforms.
BRANCH=None
BUG=None
TEST=Built and tested on nami system
Change-Id: Idc82f3d2f805b92fb3005d2f49098e55cb142e45
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
index f02acce..b8455fe 100644
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -325,8 +325,10 @@
}"
register "speed_shift_enable" = "1"
- register "tdp_psyspl2" = "90"
- register "psys_pmax" = "120"
+ register "power_limits_config" = "{
+ .tdp_psyspl2 = 90,
+ .psys_pmax = 120,
+ }"
register "tcc_offset" = "6" # TCC of 94C
device cpu_cluster 0 on