soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion support

New UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure
clock source number of PCIe root ports. This UPD array is set to clock
source number(0-6) for all the enabled PCIe root ports, invalid(0x1F)
is set for disabled PCIe root ports.

TEST= Perform the following
1. Build and boot soraka
2. Verify PCIe devices list using lspci command
3. Perform Basic Assurance Test(BAT) on soraka

Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e
Signed-off-by: Divya Chellap <>
Tested-by: build bot (Jenkins) <>
Reviewed-by: Aaron Durbin <>
Reviewed-by: Subrata Banik <>
Reviewed-by: Furquan Shaikh <>
10 files changed