commit e7fb7ce06577d88a193c8553b2d94c12eb256c58
author Divya Chellap <divya.chellappa@intel.com> Tue Dec 19 20:16:50 2017 +0530
committer Martin Roth <martinroth@google.com> Fri Dec 22 16:43:17 2017 +0000
tree e14ad6b678a80c6112dfc0f67e84ba9c1094e8ca
parent 361d197d7789f1a974eff05c7a6d7debc0929646

soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion support

New UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure
clock source number of PCIe root ports. This UPD array is set to clock
source number(0-6) for all the enabled PCIe root ports, invalid(0x1F)
is set for disabled PCIe root ports.

BUG=b:70252901
BRANCH=None
TEST= Perform the following
1. Build and boot soraka
2. Verify PCIe devices list using lspci command
3. Perform Basic Assurance Test(BAT) on soraka

Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e
Signed-off-by: Divya Chellap <divya.chellappa@intel.com>
Reviewed-on: https://review.coreboot.org/22947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/mainboard/google/fizz/devicetree.cb

diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index 1ee54aa..59a80fa 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -178,6 +178,8 @@
 	register "PcieRpAdvancedErrorReporting[2]" = "1"
 	# RP 3, Enable Latency Tolerance Reporting Mechanism
 	register "PcieRpLtrEnable[2]" = "1"
+	# RP 3 uses uses CLK SRC 0
+	register "PcieRpClkSrcNumber[2]" = "0"
 
 	# Enable Root port 4(x1) for WLAN.
 	register "PcieRpEnable[3]" = "1"
@@ -189,6 +191,8 @@
 	register "PcieRpAdvancedErrorReporting[3]" = "1"
 	# RP 4, Enable Latency Tolerance Reporting Mechanism
 	register "PcieRpLtrEnable[3]" = "1"
+	# RP 4 uses uses CLK SRC 5
+	register "PcieRpClkSrcNumber[3]" = "5"
 
 	# Enable Root port 5(x4) for NVMe.
 	register "PcieRpEnable[4]" = "1"
@@ -200,6 +204,8 @@
 	register "PcieRpAdvancedErrorReporting[4]" = "1"
 	# RP 5, Enable Latency Tolerance Reporting Mechanism
 	register "PcieRpLtrEnable[4]" = "1"
+	# RP 5 uses CLK SRC 1
+	register "PcieRpClkSrcNumber[4]" = "1"
 
 	# Enable Root port 9 for BtoB.
 	register "PcieRpEnable[8]" = "1"
@@ -211,6 +217,8 @@
 	register "PcieRpAdvancedErrorReporting[8]" = "1"
 	# RP 9, Enable Latency Tolerance Reporting Mechanism
 	register "PcieRpLtrEnable[8]" = "1"
+	# RP 9 uses uses CLK SRC 2
+	register "PcieRpClkSrcNumber[8]" = "2"
 
 	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C
 	register "usb2_ports[1]" = "USB2_PORT_MID(OC3)"		# Type-A Rear