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Shelley Chen243dc392017-03-15 15:25:48 -07001chip soc/intel/skylake
2
3 # Deep Sx states
Duncan Laurie1fe32d62017-04-10 21:02:13 -07004 register "deep_s3_enable_ac" = "0"
5 register "deep_s3_enable_dc" = "0"
6 register "deep_s5_enable_ac" = "1"
7 register "deep_s5_enable_dc" = "1"
Shelley Chen243dc392017-03-15 15:25:48 -07008 register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"
9
Shelley Chenda6e4f62017-06-29 16:13:33 -070010 # Mapping of USB port # to device
11 #+----------------+-------+-----------------------------------+
12 #| Device | Port# | Rev |
13 #+----------------+-------+-----------------------------------+
14 #| USB C | 1 | 2/3 |
15 #| USB A Rear | 2 | 2/3 |
16 #| USB A Front | 3 | 2/3 |
17 #| USB A Front | 4 | 2/3 |
18 #| USB A Rear | 5 | 2 on base celeron, 2/3 all others |
19 #| USB A Rear | 6 | 2 on base celeron, 2/3 all others |
20 #| Bluetooth | 7 | |
21 #| Daughter Board | 8 | |
22 #+----------------+-------+-----------------------------------+
23
24 # Bitmap for Wake Enable on USB attach/detach
25 register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) | \
26 USB_PORT_WAKE_ENABLE(3) | \
27 USB_PORT_WAKE_ENABLE(4) | \
28 USB_PORT_WAKE_ENABLE(5) | \
29 USB_PORT_WAKE_ENABLE(6)"
30 register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) | \
31 USB_PORT_WAKE_ENABLE(3) | \
32 USB_PORT_WAKE_ENABLE(4) | \
33 USB_PORT_WAKE_ENABLE(5) | \
34 USB_PORT_WAKE_ENABLE(6)"
35
Shelley Chen243dc392017-03-15 15:25:48 -070036 # GPE configuration
37 # Note that GPE events called out in ASL code rely on this
38 # route. i.e. If this route changes then the affected GPE
39 # offset bits also need to be changed.
40 register "gpe0_dw0" = "GPP_B"
41 register "gpe0_dw1" = "GPP_D"
42 register "gpe0_dw2" = "GPP_E"
43
44 # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
45 register "gen1_dec" = "0x00fc0801"
46 register "gen2_dec" = "0x000c0201"
47 # EC memory map range is 0x900-0x9ff
48 register "gen3_dec" = "0x00fc0901"
49
Tsai, Gaggeryb2a3ac42017-08-22 10:55:13 +080050 # Enable DPTF
51 register "dptf_enable" = "1"
52
Shelley Chen6dd9e592017-12-20 10:43:25 -080053 # Enable S0ix
54 register "s0ix_enable" = "1"
55
Shelley Chen243dc392017-03-15 15:25:48 -070056 # FSP Configuration
57 register "ProbelessTrace" = "0"
Shelley Chenc5168832017-03-21 15:04:04 -070058 register "EnableLan" = "1"
59 register "EnableSata" = "1"
60 register "SataSalpSupport" = "1"
Kane Chen91ea9f02017-12-13 11:35:54 +080061 register "SataMode" = "0"
David Wu0f829052017-12-11 14:08:11 +080062 register "SataPortsEnable[0]" = "1"
Shelley Chene8365aa2017-04-24 13:11:43 -070063 register "SataPortsEnable[1]" = "1"
Gaggery Tsaibc37c672017-09-29 13:40:04 +080064 register "SataPortsDevSlp[1]" = "1"
Shelley Chen243dc392017-03-15 15:25:48 -070065 register "EnableAzalia" = "1"
66 register "DspEnable" = "1"
67 register "IoBufferOwnership" = "3"
68 register "EnableTraceHub" = "0"
69 register "XdciEnable" = "0"
70 register "SsicPortEnable" = "0"
71 register "SmbusEnable" = "1"
72 register "Cio2Enable" = "0"
Shelley Chenc5168832017-03-21 15:04:04 -070073 register "ScsEmmcEnabled" = "0"
74 register "ScsEmmcHs400Enabled" = "0"
Shelley Chen243dc392017-03-15 15:25:48 -070075 register "ScsSdCardEnabled" = "2"
76 register "IshEnable" = "0"
77 register "PttSwitch" = "0"
78 register "InternalGfx" = "1"
79 register "SkipExtGfxScan" = "1"
80 register "Device4Enable" = "1"
81 register "HeciEnabled" = "0"
82 register "FspSkipMpInit" = "1"
83 register "SaGv" = "3"
84 register "SerialIrqConfigSirqEnable" = "1"
85 register "PmConfigSlpS3MinAssert" = "2" # 50ms
86 register "PmConfigSlpS4MinAssert" = "1" # 1s
87 register "PmConfigSlpSusMinAssert" = "1" # 500ms
88 register "PmConfigSlpAMinAssert" = "3" # 2s
89 register "PmTimerDisabled" = "1"
90 register "SendVrMbxCmd" = "1" # IMVP8 workaround
91
Rizwan Qureshibbff1572017-12-07 02:10:06 +053092 # Intersil VR c-state issue workaround
93 # send VR mailbox command for IA/GT/SA rails
94 register "IslVrCmd" = "2"
95
Shelley Chen243dc392017-03-15 15:25:48 -070096 register "pirqa_routing" = "PCH_IRQ11"
97 register "pirqb_routing" = "PCH_IRQ10"
98 register "pirqc_routing" = "PCH_IRQ11"
99 register "pirqd_routing" = "PCH_IRQ11"
100 register "pirqe_routing" = "PCH_IRQ11"
101 register "pirqf_routing" = "PCH_IRQ11"
102 register "pirqg_routing" = "PCH_IRQ11"
103 register "pirqh_routing" = "PCH_IRQ11"
104
105 # VR Settings Configuration for 4 Domains
106 #+----------------+-------+-------+-------+-------+
107 #| Domain/Setting | SA | IA | GTUS | GTS |
108 #+----------------+-------+-------+-------+-------+
109 #| Psi1Threshold | 20A | 20A | 20A | 20A |
110 #| Psi2Threshold | 4A | 5A | 5A | 5A |
111 #| Psi3Threshold | 1A | 1A | 1A | 1A |
112 #| Psi3Enable | 1 | 1 | 1 | 1 |
113 #| Psi4Enable | 1 | 1 | 1 | 1 |
114 #| ImonSlope | 0 | 0 | 0 | 0 |
115 #| ImonOffset | 0 | 0 | 0 | 0 |
116 #| IccMax | 7A | 34A | 35A | 35A |
117 #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
118 #+----------------+-------+-------+-------+-------+
119 register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
120 .vr_config_enable = 1,
121 .psi1threshold = VR_CFG_AMP(20),
122 .psi2threshold = VR_CFG_AMP(4),
123 .psi3threshold = VR_CFG_AMP(1),
124 .psi3enable = 1,
125 .psi4enable = 1,
126 .imon_slope = 0x0,
127 .imon_offset = 0x0,
128 .icc_max = VR_CFG_AMP(7),
129 .voltage_limit = 1520,
130 }"
131
132 register "domain_vr_config[VR_IA_CORE]" = "{
133 .vr_config_enable = 1,
134 .psi1threshold = VR_CFG_AMP(20),
135 .psi2threshold = VR_CFG_AMP(5),
136 .psi3threshold = VR_CFG_AMP(1),
137 .psi3enable = 1,
138 .psi4enable = 1,
139 .imon_slope = 0x0,
140 .imon_offset = 0x0,
141 .icc_max = VR_CFG_AMP(34),
142 .voltage_limit = 1520,
143 }"
144
145 register "domain_vr_config[VR_GT_UNSLICED]" = "{
146 .vr_config_enable = 1,
147 .psi1threshold = VR_CFG_AMP(20),
148 .psi2threshold = VR_CFG_AMP(5),
149 .psi3threshold = VR_CFG_AMP(1),
150 .psi3enable = 1,
151 .psi4enable = 1,
152 .imon_slope = 0x0,
153 .imon_offset = 0x0,
154 .icc_max = VR_CFG_AMP(35),
155 .voltage_limit = 1520,
156 }"
157
158 register "domain_vr_config[VR_GT_SLICED]" = "{
159 .vr_config_enable = 1,
160 .psi1threshold = VR_CFG_AMP(20),
161 .psi2threshold = VR_CFG_AMP(5),
162 .psi3threshold = VR_CFG_AMP(1),
163 .psi3enable = 1,
164 .psi4enable = 1,
165 .imon_slope = 0x0,
166 .imon_offset = 0x0,
167 .icc_max = VR_CFG_AMP(35),
168 .voltage_limit = 1520,
169 }"
170
Naresh G Solanki561f7fc2017-04-20 16:45:01 +0530171 # Enable Root port 3(x1) for LAN.
172 register "PcieRpEnable[2]" = "1"
Shelley Chen243dc392017-03-15 15:25:48 -0700173 # Enable CLKREQ#
Naresh G Solanki561f7fc2017-04-20 16:45:01 +0530174 register "PcieRpClkReqSupport[2]" = "1"
175 # RP 3 uses SRCCLKREQ0#
176 register "PcieRpClkReqNumber[2]" = "0"
Kane Chen6708d3a2017-10-11 12:39:46 +0800177 # RP 3, Enable Advanced Error Reporting
178 register "PcieRpAdvancedErrorReporting[2]" = "1"
179 # RP 3, Enable Latency Tolerance Reporting Mechanism
180 register "PcieRpLtrEnable[2]" = "1"
Divya Chellape7fb7ce2017-12-19 20:16:50 +0530181 # RP 3 uses uses CLK SRC 0
182 register "PcieRpClkSrcNumber[2]" = "0"
Naresh G Solanki561f7fc2017-04-20 16:45:01 +0530183
184 # Enable Root port 4(x1) for WLAN.
185 register "PcieRpEnable[3]" = "1"
186 # Enable CLKREQ#
187 register "PcieRpClkReqSupport[3]" = "1"
188 # RP 4 uses SRCCLKREQ5#
189 register "PcieRpClkReqNumber[3]" = "5"
Kane Chen6708d3a2017-10-11 12:39:46 +0800190 # RP 4, Enable Advanced Error Reporting
191 register "PcieRpAdvancedErrorReporting[3]" = "1"
192 # RP 4, Enable Latency Tolerance Reporting Mechanism
193 register "PcieRpLtrEnable[3]" = "1"
Divya Chellape7fb7ce2017-12-19 20:16:50 +0530194 # RP 4 uses uses CLK SRC 5
195 register "PcieRpClkSrcNumber[3]" = "5"
Naresh G Solanki561f7fc2017-04-20 16:45:01 +0530196
197 # Enable Root port 5(x4) for NVMe.
198 register "PcieRpEnable[4]" = "1"
199 # Enable CLKREQ#
200 register "PcieRpClkReqSupport[4]" = "1"
201 # RP 5 uses SRCCLKREQ1#
202 register "PcieRpClkReqNumber[4]" = "1"
Kane Chen6708d3a2017-10-11 12:39:46 +0800203 # RP 5, Enable Advanced Error Reporting
204 register "PcieRpAdvancedErrorReporting[4]" = "1"
205 # RP 5, Enable Latency Tolerance Reporting Mechanism
206 register "PcieRpLtrEnable[4]" = "1"
Divya Chellape7fb7ce2017-12-19 20:16:50 +0530207 # RP 5 uses CLK SRC 1
208 register "PcieRpClkSrcNumber[4]" = "1"
Naresh G Solanki561f7fc2017-04-20 16:45:01 +0530209
210 # Enable Root port 9 for BtoB.
211 register "PcieRpEnable[8]" = "1"
212 # Enable CLKREQ#
213 register "PcieRpClkReqSupport[8]" = "1"
214 # RP 9 uses SRCCLKREQ2#
215 register "PcieRpClkReqNumber[8]" = "2"
Kane Chen6708d3a2017-10-11 12:39:46 +0800216 # RP 9, Enable Advanced Error Reporting
217 register "PcieRpAdvancedErrorReporting[8]" = "1"
218 # RP 9, Enable Latency Tolerance Reporting Mechanism
219 register "PcieRpLtrEnable[8]" = "1"
Divya Chellape7fb7ce2017-12-19 20:16:50 +0530220 # RP 9 uses uses CLK SRC 2
221 register "PcieRpClkSrcNumber[8]" = "2"
Shelley Chen243dc392017-03-15 15:25:48 -0700222
Shelley Chenc5168832017-03-21 15:04:04 -0700223 register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C
224 register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-A Rear
225 register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Front
226 register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A Front
227 register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # Type-A Rear
228 register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Rear
229 register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
230 register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A 2.0 / Debug
231 register "usb2_ports[8]" = "USB2_PORT_EMPTY" # H1 (disconnected)
Shelley Chen243dc392017-03-15 15:25:48 -0700232
Shelley Chenc5168832017-03-21 15:04:04 -0700233 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C
234 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear
235 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front
236 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front
Naresh G Solanki561f7fc2017-04-20 16:45:01 +0530237 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear
238 register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear
Shelley Chen243dc392017-03-15 15:25:48 -0700239
Shelley Chenc5168832017-03-21 15:04:04 -0700240 register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # HDMI CEC
241 register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM
242 register "i2c_voltage[2]" = "I2C_VOLTAGE_3V3" # Debug
Shelley Chen243dc392017-03-15 15:25:48 -0700243 register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio
244
Shelley Chen5aa64b92017-06-09 13:05:29 -0700245 # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM
246 # communication before memory is up.
247 register "gspi[0]" = "{
248 .speed_mhz = 1,
249 .early_init = 1,
250 }"
251
Shelley Chen243dc392017-03-15 15:25:48 -0700252 # Must leave UART0 enabled or SD/eMMC will not work as PCI
253 register "SerialIoDevMode" = "{
Shelley Chen5537f022017-11-22 16:55:27 -0800254 [PchSerialIoIndexI2C0] = PchSerialIoDisabled,
255 [PchSerialIoIndexI2C1] = PchSerialIoDisabled,
256 [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
Shelley Chenc5168832017-03-21 15:04:04 -0700257 [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
258 [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
Shelley Chen243dc392017-03-15 15:25:48 -0700259 [PchSerialIoIndexI2C5] = PchSerialIoPci,
260 [PchSerialIoIndexSpi0] = PchSerialIoPci,
Shelley Chenc5168832017-03-21 15:04:04 -0700261 [PchSerialIoIndexSpi1] = PchSerialIoDisabled,
Shelley Chen243dc392017-03-15 15:25:48 -0700262 [PchSerialIoIndexUart0] = PchSerialIoPci,
263 [PchSerialIoIndexUart1] = PchSerialIoDisabled,
264 [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
265 }"
266
267 register "speed_shift_enable" = "1"
Shelley Chen8c81c6a2017-06-29 14:58:59 -0700268 register "tdp_psyspl2" = "90"
Shelley Chen243dc392017-03-15 15:25:48 -0700269 register "tcc_offset" = "10" # TCC of 90C
270
271 # Use default SD card detect GPIO configuration
Shelley Chenc5168832017-03-21 15:04:04 -0700272 register "sdcard_cd_gpio_default" = "GPP_A7"
Shelley Chen243dc392017-03-15 15:25:48 -0700273
Subrata Banikc204aaa2017-08-17 15:49:58 +0530274 # Lock Down
275 register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
276
Shelley Chen243dc392017-03-15 15:25:48 -0700277 device cpu_cluster 0 on
278 device lapic 0 on end
279 end
280 device domain 0 on
281 device pci 00.0 on end # Host Bridge
282 device pci 02.0 on end # Integrated Graphics Device
283 device pci 14.0 on end # USB xHCI
284 device pci 14.1 off end # USB xDCI (OTG)
285 device pci 14.2 on end # Thermal Subsystem
Shelley Chen5537f022017-11-22 16:55:27 -0800286 device pci 15.0 off end # I2C #0
287 device pci 15.1 off end # I2C #1
288 device pci 15.2 off end # I2C #2
289 device pci 15.3 off end # I2C #3
Shelley Chen243dc392017-03-15 15:25:48 -0700290 device pci 16.0 on end # Management Engine Interface 1
291 device pci 16.1 off end # Management Engine Interface 2
292 device pci 16.2 off end # Management Engine IDE-R
293 device pci 16.3 off end # Management Engine KT Redirection
294 device pci 16.4 off end # Management Engine Interface 3
Shelley Chenc5168832017-03-21 15:04:04 -0700295 device pci 17.0 on end # SATA
Shelley Chen243dc392017-03-15 15:25:48 -0700296 device pci 19.0 on end # UART #2
297 device pci 19.1 on
Kevin Cheng2a6f4ae2017-06-06 10:37:59 +0800298 chip drivers/i2c/generic
299 register "hid" = ""10EC5663""
300 register "name" = ""RT53""
301 register "desc" = ""Realtek RT5663""
302 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)"
303 device i2c 13 on end
304 end
Shelley Chen243dc392017-03-15 15:25:48 -0700305 end # I2C #5
Shelley Chenc5168832017-03-21 15:04:04 -0700306 device pci 19.2 off end # I2C #4
Gaggery Tsai2ecf3f82017-11-02 09:58:06 +0800307 device pci 1c.0 on # PCI Express Port 1
308 chip drivers/net
Gaggery Tsaid7de7bc2017-12-20 13:12:57 +0800309 register "customized_leds" = "0x0fa5"
Gaggery Tsai61c817d2017-11-23 13:23:57 +0800310 register "wake" = "GPE0_PCI_EXP"
Gaggery Tsai2ecf3f82017-11-02 09:58:06 +0800311 device pci 00.0 on end
312 end
313 end # PCI Express Port 1
Naresh G Solanki561f7fc2017-04-20 16:45:01 +0530314 device pci 1c.1 off end # PCI Express Port 2
Gaggery Tsai2ecf3f82017-11-02 09:58:06 +0800315 # PCI Express Port 3 for LAN, but will be swapped to port 1
316 device pci 1c.2 on end
Naresh G Solanki561f7fc2017-04-20 16:45:01 +0530317 device pci 1c.3 on
Shelley Chen243dc392017-03-15 15:25:48 -0700318 chip drivers/intel/wifi
319 register "wake" = "GPE0_PCI_EXP"
320 device pci 00.0 on end
321 end
Naresh G Solanki561f7fc2017-04-20 16:45:01 +0530322 end # PCI Express Port 4 for WLAN
323 device pci 1c.4 on end # PCI Express Port 5 for NVMe
Shelley Chen243dc392017-03-15 15:25:48 -0700324 device pci 1c.5 off end # PCI Express Port 6
325 device pci 1c.6 off end # PCI Express Port 7
326 device pci 1c.7 off end # PCI Express Port 8
David Wu5f7fa722017-12-11 14:40:36 +0800327 device pci 1d.0 on # PCI Express Port 9 for 2nd LAN
328 chip drivers/net
Gaggery Tsaid7de7bc2017-12-20 13:12:57 +0800329 register "customized_leds" = "0x0fa5"
David Wu5f7fa722017-12-11 14:40:36 +0800330 device pci 00.0 on end
331 end
332 end # PCI Express Port 9 for BtoB
Shelley Chen243dc392017-03-15 15:25:48 -0700333 device pci 1d.1 off end # PCI Express Port 10
334 device pci 1d.2 off end # PCI Express Port 11
335 device pci 1d.3 off end # PCI Express Port 12
336 device pci 1e.0 on end # UART #0
337 device pci 1e.1 off end # UART #1
Shelley Chen5aa64b92017-06-09 13:05:29 -0700338 device pci 1e.2 on
339 chip drivers/spi/acpi
340 register "hid" = "ACPI_DT_NAMESPACE_HID"
341 register "compat_string" = ""google,cr50""
342 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"
343 device spi 0 on end
344 end
345 end # GSPI #0
Shelley Chenc5168832017-03-21 15:04:04 -0700346 device pci 1e.3 off end # GSPI #1
347 device pci 1e.4 off end # eMMC
Shelley Chen243dc392017-03-15 15:25:48 -0700348 device pci 1e.5 off end # SDIO
349 device pci 1e.6 on end # SDCard
350 device pci 1f.0 on
351 chip ec/google/chromeec
352 device pnp 0c09.0 on end
353 end
354 end # LPC Interface
355 device pci 1f.1 on end # P2SB
356 device pci 1f.2 on end # Power Management Controller
357 device pci 1f.3 on end # Intel HDA
358 device pci 1f.4 on end # SMBus
359 device pci 1f.5 on end # PCH SPI
360 device pci 1f.6 off end # GbE
361 end
362end