Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # Deep Sx states |
Duncan Laurie | 1fe32d6 | 2017-04-10 21:02:13 -0700 | [diff] [blame] | 4 | register "deep_s3_enable_ac" = "0" |
| 5 | register "deep_s3_enable_dc" = "0" |
| 6 | register "deep_s5_enable_ac" = "1" |
| 7 | register "deep_s5_enable_dc" = "1" |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 8 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" |
| 9 | |
| 10 | # GPE configuration |
| 11 | # Note that GPE events called out in ASL code rely on this |
| 12 | # route. i.e. If this route changes then the affected GPE |
| 13 | # offset bits also need to be changed. |
| 14 | register "gpe0_dw0" = "GPP_B" |
| 15 | register "gpe0_dw1" = "GPP_D" |
| 16 | register "gpe0_dw2" = "GPP_E" |
| 17 | |
| 18 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 19 | register "gen1_dec" = "0x00fc0801" |
| 20 | register "gen2_dec" = "0x000c0201" |
| 21 | # EC memory map range is 0x900-0x9ff |
| 22 | register "gen3_dec" = "0x00fc0901" |
| 23 | |
Tsai, Gaggery | b2a3ac4 | 2017-08-22 10:55:13 +0800 | [diff] [blame^] | 24 | # Enable DPTF |
| 25 | register "dptf_enable" = "1" |
| 26 | |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 27 | # FSP Configuration |
| 28 | register "ProbelessTrace" = "0" |
Shelley Chen | c516883 | 2017-03-21 15:04:04 -0700 | [diff] [blame] | 29 | register "EnableLan" = "1" |
| 30 | register "EnableSata" = "1" |
| 31 | register "SataSalpSupport" = "1" |
| 32 | register "SataMode" = "1" |
| 33 | register "SataPortsEnable[0]" = "1" |
Shelley Chen | e8365aa | 2017-04-24 13:11:43 -0700 | [diff] [blame] | 34 | register "SataPortsEnable[1]" = "1" |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 35 | register "EnableAzalia" = "1" |
| 36 | register "DspEnable" = "1" |
| 37 | register "IoBufferOwnership" = "3" |
| 38 | register "EnableTraceHub" = "0" |
| 39 | register "XdciEnable" = "0" |
| 40 | register "SsicPortEnable" = "0" |
| 41 | register "SmbusEnable" = "1" |
| 42 | register "Cio2Enable" = "0" |
Shelley Chen | c516883 | 2017-03-21 15:04:04 -0700 | [diff] [blame] | 43 | register "ScsEmmcEnabled" = "0" |
| 44 | register "ScsEmmcHs400Enabled" = "0" |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 45 | register "ScsSdCardEnabled" = "2" |
| 46 | register "IshEnable" = "0" |
| 47 | register "PttSwitch" = "0" |
| 48 | register "InternalGfx" = "1" |
| 49 | register "SkipExtGfxScan" = "1" |
| 50 | register "Device4Enable" = "1" |
| 51 | register "HeciEnabled" = "0" |
| 52 | register "FspSkipMpInit" = "1" |
| 53 | register "SaGv" = "3" |
| 54 | register "SerialIrqConfigSirqEnable" = "1" |
| 55 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 56 | register "PmConfigSlpS4MinAssert" = "1" # 1s |
| 57 | register "PmConfigSlpSusMinAssert" = "1" # 500ms |
| 58 | register "PmConfigSlpAMinAssert" = "3" # 2s |
| 59 | register "PmTimerDisabled" = "1" |
| 60 | register "SendVrMbxCmd" = "1" # IMVP8 workaround |
| 61 | |
| 62 | register "pirqa_routing" = "PCH_IRQ11" |
| 63 | register "pirqb_routing" = "PCH_IRQ10" |
| 64 | register "pirqc_routing" = "PCH_IRQ11" |
| 65 | register "pirqd_routing" = "PCH_IRQ11" |
| 66 | register "pirqe_routing" = "PCH_IRQ11" |
| 67 | register "pirqf_routing" = "PCH_IRQ11" |
| 68 | register "pirqg_routing" = "PCH_IRQ11" |
| 69 | register "pirqh_routing" = "PCH_IRQ11" |
| 70 | |
| 71 | # VR Settings Configuration for 4 Domains |
| 72 | #+----------------+-------+-------+-------+-------+ |
| 73 | #| Domain/Setting | SA | IA | GTUS | GTS | |
| 74 | #+----------------+-------+-------+-------+-------+ |
| 75 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 76 | #| Psi2Threshold | 4A | 5A | 5A | 5A | |
| 77 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 78 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 79 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 80 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 81 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 82 | #| IccMax | 7A | 34A | 35A | 35A | |
| 83 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 84 | #+----------------+-------+-------+-------+-------+ |
| 85 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 86 | .vr_config_enable = 1, |
| 87 | .psi1threshold = VR_CFG_AMP(20), |
| 88 | .psi2threshold = VR_CFG_AMP(4), |
| 89 | .psi3threshold = VR_CFG_AMP(1), |
| 90 | .psi3enable = 1, |
| 91 | .psi4enable = 1, |
| 92 | .imon_slope = 0x0, |
| 93 | .imon_offset = 0x0, |
| 94 | .icc_max = VR_CFG_AMP(7), |
| 95 | .voltage_limit = 1520, |
| 96 | }" |
| 97 | |
| 98 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 99 | .vr_config_enable = 1, |
| 100 | .psi1threshold = VR_CFG_AMP(20), |
| 101 | .psi2threshold = VR_CFG_AMP(5), |
| 102 | .psi3threshold = VR_CFG_AMP(1), |
| 103 | .psi3enable = 1, |
| 104 | .psi4enable = 1, |
| 105 | .imon_slope = 0x0, |
| 106 | .imon_offset = 0x0, |
| 107 | .icc_max = VR_CFG_AMP(34), |
| 108 | .voltage_limit = 1520, |
| 109 | }" |
| 110 | |
| 111 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 112 | .vr_config_enable = 1, |
| 113 | .psi1threshold = VR_CFG_AMP(20), |
| 114 | .psi2threshold = VR_CFG_AMP(5), |
| 115 | .psi3threshold = VR_CFG_AMP(1), |
| 116 | .psi3enable = 1, |
| 117 | .psi4enable = 1, |
| 118 | .imon_slope = 0x0, |
| 119 | .imon_offset = 0x0, |
| 120 | .icc_max = VR_CFG_AMP(35), |
| 121 | .voltage_limit = 1520, |
| 122 | }" |
| 123 | |
| 124 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 125 | .vr_config_enable = 1, |
| 126 | .psi1threshold = VR_CFG_AMP(20), |
| 127 | .psi2threshold = VR_CFG_AMP(5), |
| 128 | .psi3threshold = VR_CFG_AMP(1), |
| 129 | .psi3enable = 1, |
| 130 | .psi4enable = 1, |
| 131 | .imon_slope = 0x0, |
| 132 | .imon_offset = 0x0, |
| 133 | .icc_max = VR_CFG_AMP(35), |
| 134 | .voltage_limit = 1520, |
| 135 | }" |
| 136 | |
Naresh G Solanki | 561f7fc | 2017-04-20 16:45:01 +0530 | [diff] [blame] | 137 | # Enable Root port 3(x1) for LAN. |
| 138 | register "PcieRpEnable[2]" = "1" |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 139 | # Enable CLKREQ# |
Naresh G Solanki | 561f7fc | 2017-04-20 16:45:01 +0530 | [diff] [blame] | 140 | register "PcieRpClkReqSupport[2]" = "1" |
| 141 | # RP 3 uses SRCCLKREQ0# |
| 142 | register "PcieRpClkReqNumber[2]" = "0" |
| 143 | |
| 144 | # Enable Root port 4(x1) for WLAN. |
| 145 | register "PcieRpEnable[3]" = "1" |
| 146 | # Enable CLKREQ# |
| 147 | register "PcieRpClkReqSupport[3]" = "1" |
| 148 | # RP 4 uses SRCCLKREQ5# |
| 149 | register "PcieRpClkReqNumber[3]" = "5" |
| 150 | |
| 151 | # Enable Root port 5(x4) for NVMe. |
| 152 | register "PcieRpEnable[4]" = "1" |
| 153 | # Enable CLKREQ# |
| 154 | register "PcieRpClkReqSupport[4]" = "1" |
| 155 | # RP 5 uses SRCCLKREQ1# |
| 156 | register "PcieRpClkReqNumber[4]" = "1" |
| 157 | |
| 158 | # Enable Root port 9 for BtoB. |
| 159 | register "PcieRpEnable[8]" = "1" |
| 160 | # Enable CLKREQ# |
| 161 | register "PcieRpClkReqSupport[8]" = "1" |
| 162 | # RP 9 uses SRCCLKREQ2# |
| 163 | register "PcieRpClkReqNumber[8]" = "2" |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 164 | |
Shelley Chen | c516883 | 2017-03-21 15:04:04 -0700 | [diff] [blame] | 165 | register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C |
| 166 | register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-A Rear |
| 167 | register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Front |
| 168 | register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A Front |
| 169 | register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # Type-A Rear |
| 170 | register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Rear |
| 171 | register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth |
| 172 | register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A 2.0 / Debug |
| 173 | register "usb2_ports[8]" = "USB2_PORT_EMPTY" # H1 (disconnected) |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 174 | |
Shelley Chen | c516883 | 2017-03-21 15:04:04 -0700 | [diff] [blame] | 175 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C |
| 176 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear |
| 177 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front |
| 178 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front |
Naresh G Solanki | 561f7fc | 2017-04-20 16:45:01 +0530 | [diff] [blame] | 179 | register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear |
| 180 | register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 181 | |
Shelley Chen | c516883 | 2017-03-21 15:04:04 -0700 | [diff] [blame] | 182 | register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # HDMI CEC |
| 183 | register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM |
| 184 | register "i2c_voltage[2]" = "I2C_VOLTAGE_3V3" # Debug |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 185 | register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio |
| 186 | |
Shelley Chen | 5aa64b9 | 2017-06-09 13:05:29 -0700 | [diff] [blame] | 187 | # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM |
| 188 | # communication before memory is up. |
| 189 | register "gspi[0]" = "{ |
| 190 | .speed_mhz = 1, |
| 191 | .early_init = 1, |
| 192 | }" |
| 193 | |
Shelley Chen | db287aa | 2017-06-09 12:56:08 -0700 | [diff] [blame] | 194 | # Configure I2C1 for cr50 TPM. Early init is required to set up a BAR |
| 195 | # for TPM communication before memory is up. |
| 196 | register "i2c[1]" = "{ |
| 197 | .early_init = 1, |
| 198 | }" |
| 199 | |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 200 | # Must leave UART0 enabled or SD/eMMC will not work as PCI |
| 201 | register "SerialIoDevMode" = "{ |
| 202 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 203 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 204 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
Shelley Chen | c516883 | 2017-03-21 15:04:04 -0700 | [diff] [blame] | 205 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
| 206 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 207 | [PchSerialIoIndexI2C5] = PchSerialIoPci, |
| 208 | [PchSerialIoIndexSpi0] = PchSerialIoPci, |
Shelley Chen | c516883 | 2017-03-21 15:04:04 -0700 | [diff] [blame] | 209 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 210 | [PchSerialIoIndexUart0] = PchSerialIoPci, |
| 211 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, |
| 212 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, |
| 213 | }" |
| 214 | |
| 215 | register "speed_shift_enable" = "1" |
Shelley Chen | 8c81c6a | 2017-06-29 14:58:59 -0700 | [diff] [blame] | 216 | register "tdp_psyspl2" = "90" |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 217 | register "tcc_offset" = "10" # TCC of 90C |
| 218 | |
| 219 | # Use default SD card detect GPIO configuration |
Shelley Chen | c516883 | 2017-03-21 15:04:04 -0700 | [diff] [blame] | 220 | register "sdcard_cd_gpio_default" = "GPP_A7" |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 221 | |
Subrata Banik | c204aaa | 2017-08-17 15:49:58 +0530 | [diff] [blame] | 222 | # Lock Down |
| 223 | register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" |
| 224 | |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 225 | device cpu_cluster 0 on |
| 226 | device lapic 0 on end |
| 227 | end |
| 228 | device domain 0 on |
| 229 | device pci 00.0 on end # Host Bridge |
| 230 | device pci 02.0 on end # Integrated Graphics Device |
| 231 | device pci 14.0 on end # USB xHCI |
| 232 | device pci 14.1 off end # USB xDCI (OTG) |
| 233 | device pci 14.2 on end # Thermal Subsystem |
| 234 | device pci 15.0 on |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 235 | end # I2C #0 |
Shelley Chen | db287aa | 2017-06-09 12:56:08 -0700 | [diff] [blame] | 236 | device pci 15.1 on |
| 237 | chip drivers/i2c/tpm |
| 238 | register "hid" = ""GOOG0005"" |
| 239 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" |
| 240 | device i2c 50 on end |
| 241 | end |
| 242 | end # I2C #1 |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 243 | device pci 15.2 on end # I2C #2 |
Shelley Chen | c516883 | 2017-03-21 15:04:04 -0700 | [diff] [blame] | 244 | device pci 15.3 off |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 245 | end # I2C #3 |
| 246 | device pci 16.0 on end # Management Engine Interface 1 |
| 247 | device pci 16.1 off end # Management Engine Interface 2 |
| 248 | device pci 16.2 off end # Management Engine IDE-R |
| 249 | device pci 16.3 off end # Management Engine KT Redirection |
| 250 | device pci 16.4 off end # Management Engine Interface 3 |
Shelley Chen | c516883 | 2017-03-21 15:04:04 -0700 | [diff] [blame] | 251 | device pci 17.0 on end # SATA |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 252 | device pci 19.0 on end # UART #2 |
| 253 | device pci 19.1 on |
Kevin Cheng | 2a6f4ae | 2017-06-06 10:37:59 +0800 | [diff] [blame] | 254 | chip drivers/i2c/generic |
| 255 | register "hid" = ""10EC5663"" |
| 256 | register "name" = ""RT53"" |
| 257 | register "desc" = ""Realtek RT5663"" |
| 258 | register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)" |
| 259 | device i2c 13 on end |
| 260 | end |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 261 | end # I2C #5 |
Shelley Chen | c516883 | 2017-03-21 15:04:04 -0700 | [diff] [blame] | 262 | device pci 19.2 off end # I2C #4 |
Shelley Chen | f49785e | 2017-05-02 16:52:27 -0700 | [diff] [blame] | 263 | device pci 1c.0 on end # PCI Express Port 1 |
Naresh G Solanki | 561f7fc | 2017-04-20 16:45:01 +0530 | [diff] [blame] | 264 | device pci 1c.1 off end # PCI Express Port 2 |
| 265 | device pci 1c.2 on end # PCI Express Port 3 for LAN |
| 266 | device pci 1c.3 on |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 267 | chip drivers/intel/wifi |
| 268 | register "wake" = "GPE0_PCI_EXP" |
| 269 | device pci 00.0 on end |
| 270 | end |
Naresh G Solanki | 561f7fc | 2017-04-20 16:45:01 +0530 | [diff] [blame] | 271 | end # PCI Express Port 4 for WLAN |
| 272 | device pci 1c.4 on end # PCI Express Port 5 for NVMe |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 273 | device pci 1c.5 off end # PCI Express Port 6 |
| 274 | device pci 1c.6 off end # PCI Express Port 7 |
| 275 | device pci 1c.7 off end # PCI Express Port 8 |
Naresh G Solanki | 561f7fc | 2017-04-20 16:45:01 +0530 | [diff] [blame] | 276 | device pci 1d.0 on end # PCI Express Port 9 for BtoB |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 277 | device pci 1d.1 off end # PCI Express Port 10 |
| 278 | device pci 1d.2 off end # PCI Express Port 11 |
| 279 | device pci 1d.3 off end # PCI Express Port 12 |
| 280 | device pci 1e.0 on end # UART #0 |
| 281 | device pci 1e.1 off end # UART #1 |
Shelley Chen | 5aa64b9 | 2017-06-09 13:05:29 -0700 | [diff] [blame] | 282 | device pci 1e.2 on |
| 283 | chip drivers/spi/acpi |
| 284 | register "hid" = "ACPI_DT_NAMESPACE_HID" |
| 285 | register "compat_string" = ""google,cr50"" |
| 286 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" |
| 287 | device spi 0 on end |
| 288 | end |
| 289 | end # GSPI #0 |
Shelley Chen | c516883 | 2017-03-21 15:04:04 -0700 | [diff] [blame] | 290 | device pci 1e.3 off end # GSPI #1 |
| 291 | device pci 1e.4 off end # eMMC |
Shelley Chen | 243dc39 | 2017-03-15 15:25:48 -0700 | [diff] [blame] | 292 | device pci 1e.5 off end # SDIO |
| 293 | device pci 1e.6 on end # SDCard |
| 294 | device pci 1f.0 on |
| 295 | chip ec/google/chromeec |
| 296 | device pnp 0c09.0 on end |
| 297 | end |
| 298 | end # LPC Interface |
| 299 | device pci 1f.1 on end # P2SB |
| 300 | device pci 1f.2 on end # Power Management Controller |
| 301 | device pci 1f.3 on end # Intel HDA |
| 302 | device pci 1f.4 on end # SMBus |
| 303 | device pci 1f.5 on end # PCH SPI |
| 304 | device pci 1f.6 off end # GbE |
| 305 | end |
| 306 | end |