Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 1 | config SOC_INTEL_METEORLAKE |
| 2 | bool |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 3 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 4 | select ARCH_X86 |
| 5 | select BOOT_DEVICE_SUPPORTS_WRITES |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 6 | select CACHE_MRC_SETTINGS |
| 7 | select CPU_INTEL_COMMON |
Subrata Banik | 1f5154e | 2022-12-06 18:21:50 +0530 | [diff] [blame] | 8 | select CPU_INTEL_COMMON_VOLTAGE |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 9 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
| 10 | select CPU_SUPPORTS_INTEL_TME |
| 11 | select CPU_SUPPORTS_PM_TIMER_EMULATION |
Matt DeVillier | decbf7b | 2023-01-18 18:58:38 -0600 | [diff] [blame] | 12 | select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS |
Subrata Banik | e96993d | 2022-07-09 22:06:45 +0000 | [diff] [blame] | 13 | select DEFAULT_X2APIC_LATE_WORKAROUND |
Saurabh Mishra | 16ba8e1 | 2022-11-22 13:35:08 +0530 | [diff] [blame] | 14 | select DISPLAY_FSP_VERSION_INFO_2 |
Ravi Sarawadi | e02fd83 | 2022-05-08 00:27:31 -0700 | [diff] [blame] | 15 | select DRIVERS_USB_ACPI |
Sean Rhodes | 7bbc9a5 | 2022-07-18 11:31:00 +0100 | [diff] [blame] | 16 | select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 17 | select FSP_COMPRESS_FSP_S_LZ4 |
| 18 | select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 19 | select FSP_M_XIP |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 20 | select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 |
Subrata Banik | e88bee7 | 2022-06-27 16:51:44 +0530 | [diff] [blame] | 21 | select FSP_USES_CB_DEBUG_EVENT_HANDLER |
| 22 | select FSPS_HAS_ARCH_UPD |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 23 | select GENERIC_GPIO_LIB |
Subrata Banik | e88bee7 | 2022-06-27 16:51:44 +0530 | [diff] [blame] | 24 | select HAVE_DEBUG_RAM_SETUP |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 25 | select HAVE_FSP_GOP |
Eran Mitrani | 222903e | 2022-12-19 11:27:10 -0800 | [diff] [blame] | 26 | select HAVE_HYPERTHREADING |
Subrata Banik | c0f4b12 | 2022-12-06 14:03:07 +0530 | [diff] [blame] | 27 | select HAVE_INTEL_COMPLIANCE_TEST_MODE |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 28 | select HAVE_SMI_HANDLER |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 29 | select IDT_IN_EVERY_STAGE |
Subrata Banik | 0d6d228 | 2022-07-09 22:17:02 +0000 | [diff] [blame] | 30 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 31 | select INTEL_GMA_ACPI |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 32 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
Dinesh Gehlot | 0d76a30 | 2022-12-09 07:24:08 +0000 | [diff] [blame] | 33 | select INTEL_GMA_OPREGION_2_1 |
Subrata Banik | 0d6d228 | 2022-07-09 22:17:02 +0000 | [diff] [blame] | 34 | select IOAPIC |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 35 | select MICROCODE_BLOB_UNDISCLOSED |
Subrata Banik | a247319 | 2023-02-22 13:03:04 +0000 | [diff] [blame] | 36 | select MP_SERVICES_PPI_V2 |
Subrata Banik | 0d6d228 | 2022-07-09 22:17:02 +0000 | [diff] [blame] | 37 | select MRC_SETTINGS_PROTECT |
Subrata Banik | 0d6d228 | 2022-07-09 22:17:02 +0000 | [diff] [blame] | 38 | select PARALLEL_MP_AP_WORK |
Kane Chen | 70c6fb4 | 2023-07-12 19:11:41 +0800 | [diff] [blame] | 39 | select PCIE_CLOCK_CONTROL_THROUGH_P2SB |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 40 | select PLATFORM_USES_FSP2_3 |
| 41 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 42 | select SOC_INTEL_COMMON |
Ravi Sarawadi | e02fd83 | 2022-05-08 00:27:31 -0700 | [diff] [blame] | 43 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 44 | select SOC_INTEL_COMMON_BLOCK |
Ravi Sarawadi | e02fd83 | 2022-05-08 00:27:31 -0700 | [diff] [blame] | 45 | select SOC_INTEL_COMMON_BLOCK_ACPI |
| 46 | select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC |
Sridhar Siricilla | d1237da | 2022-12-09 01:13:45 +0530 | [diff] [blame] | 47 | select SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID |
Ravi Sarawadi | e02fd83 | 2022-05-08 00:27:31 -0700 | [diff] [blame] | 48 | select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO |
Subrata Banik | 2a2488f | 2022-12-05 20:28:42 +0530 | [diff] [blame] | 49 | select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT |
Ravi Sarawadi | e02fd83 | 2022-05-08 00:27:31 -0700 | [diff] [blame] | 50 | select SOC_INTEL_COMMON_BLOCK_ACPI_PEP |
| 51 | select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 52 | select SOC_INTEL_COMMON_BLOCK_CAR |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 53 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Subrata Banik | 00b682e | 2022-09-14 17:58:51 -0700 | [diff] [blame] | 54 | select SOC_INTEL_COMMON_BLOCK_CNVI |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 55 | select SOC_INTEL_COMMON_BLOCK_CPU |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 56 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
| 57 | select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE |
| 58 | select SOC_INTEL_COMMON_BLOCK_DTT |
| 59 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
Subrata Banik | 247dd0e | 2023-03-16 18:31:13 +0530 | [diff] [blame] | 60 | select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY |
Subrata Banik | bae1de1 | 2022-07-21 13:43:37 +0000 | [diff] [blame] | 61 | select SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR |
Jamie Ryu | b6c32d7 | 2022-08-03 01:13:33 -0700 | [diff] [blame] | 62 | select SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 63 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 64 | select SOC_INTEL_COMMON_BLOCK_HDA |
Subrata Banik | 98b6967 | 2022-11-23 14:46:16 +0530 | [diff] [blame] | 65 | select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 66 | select SOC_INTEL_COMMON_BLOCK_IPU |
| 67 | select SOC_INTEL_COMMON_BLOCK_IOE_P2SB |
Kapil Porwal | cca3c90 | 2022-12-19 23:57:15 +0530 | [diff] [blame] | 68 | select SOC_INTEL_COMMON_BLOCK_IRQ |
Dinesh Gehlot | ef2e4fc | 2023-02-20 13:15:13 +0000 | [diff] [blame] | 69 | select SOC_INTEL_COMMON_BLOCK_ME_SPEC_18 |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 70 | select SOC_INTEL_COMMON_BLOCK_MEMINIT |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 71 | select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 |
| 72 | select SOC_INTEL_COMMON_BLOCK_PMC_EPOC |
| 73 | select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 74 | select SOC_INTEL_COMMON_BLOCK_SA |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 75 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 76 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 77 | select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 78 | select SOC_INTEL_COMMON_BLOCK_XHCI |
| 79 | select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG |
| 80 | select SOC_INTEL_COMMON_BASECODE |
Subrata Banik | 30a0114 | 2023-03-22 00:35:42 +0530 | [diff] [blame] | 81 | select SOC_INTEL_COMMON_BASECODE_RAMTOP |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 82 | select SOC_INTEL_COMMON_FSP_RESET |
Angel Pons | eb90c51 | 2022-07-18 14:41:24 +0200 | [diff] [blame] | 83 | select SOC_INTEL_COMMON_PCH_CLIENT |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 84 | select SOC_INTEL_COMMON_RESET |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 85 | select SOC_INTEL_COMMON_BLOCK_IOC |
Pratikkumar Prajapati | aa15ae0 | 2023-08-30 10:40:29 -0700 | [diff] [blame] | 86 | select SOC_INTEL_CRASHLOG |
Krishna Prasad Bhat | 4b224cb | 2023-06-26 15:34:08 +0530 | [diff] [blame] | 87 | select SOC_INTEL_CSE_LITE_PSR if MAINBOARD_HAS_CHROMEOS |
Subrata Banik | 3879334 | 2023-04-19 18:38:03 +0530 | [diff] [blame] | 88 | select SOC_INTEL_CSE_SEND_EOP_LATE if !MAINBOARD_HAS_CHROMEOS |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 89 | select SOC_INTEL_CSE_SET_EOP |
Pratikkumar Prajapati | aa15ae0 | 2023-08-30 10:40:29 -0700 | [diff] [blame] | 90 | select SOC_INTEL_IOE_DIE_SUPPORT |
Wonkyu Kim | a888489 | 2022-08-10 14:10:03 -0700 | [diff] [blame] | 91 | select SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 92 | select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 93 | select SSE2 |
| 94 | select SUPPORT_CPU_UCODE_IN_CBFS |
Anil Kumar | ab1605e | 2023-09-14 14:48:21 -0700 | [diff] [blame] | 95 | select TME_KEY_REGENERATION_ON_WARM_BOOT |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 96 | select TSC_MONOTONIC_TIMER |
| 97 | select UDELAY_TSC |
Ronak Kanabar | 8e38a67 | 2023-06-08 16:43:08 +0530 | [diff] [blame] | 98 | select UDK_202302_BINDING |
Subrata Banik | 2921a22 | 2023-02-28 10:08:27 +0000 | [diff] [blame] | 99 | select X86_CLFLUSH_CAR |
Subrata Banik | 6a22c5f | 2022-11-21 17:39:57 +0530 | [diff] [blame] | 100 | select X86_INIT_NEED_1_SIPI |
Pratikkumar Prajapati | 20ce901 | 2022-12-19 17:41:39 -0800 | [diff] [blame] | 101 | select INTEL_KEYLOCKER |
Elyes Haouas | 2f872e9 | 2023-07-21 07:47:00 +0200 | [diff] [blame] | 102 | help |
| 103 | Intel Meteorlake support. Mainboards should specify the SoC |
| 104 | type using the `SOC_INTEL_METEORLAKE_*` options instead |
| 105 | of selecting this option directly. |
| 106 | |
| 107 | config SOC_INTEL_METEORLAKE_U_H |
| 108 | bool |
| 109 | select SOC_INTEL_METEORLAKE |
| 110 | help |
| 111 | Choose this option if your mainboard has a MTL-U (9W or 15W) |
| 112 | or MTL-H (28W or 45W) SoC. |
| 113 | |
| 114 | Note, the MTL-U/H-Processor Line offered in a 1-Chip Platform |
| 115 | that includes the Compute, SOC, GT, and IOE tile on the same |
| 116 | package. |
| 117 | |
| 118 | config SOC_INTEL_METEORLAKE_S |
| 119 | bool |
| 120 | select SOC_INTEL_METEORLAKE |
| 121 | help |
| 122 | Choose this option if your mainboard has a MTL-S (35W or 65W) SoC. |
| 123 | Note, MTL-S SoC combines Compute, GFX, SoC, IOE and PCH die. |
| 124 | |
Subrata Banik | c02dd3f | 2023-09-15 23:05:48 +0530 | [diff] [blame] | 125 | config SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON |
| 126 | bool |
| 127 | default n |
| 128 | help |
| 129 | Choose this option if your mainboard has a Meteor Lake pre-production |
| 130 | silicon. Typically known as engineering samples (like ES). This type |
| 131 | of the silicon are very common for early platform development. |
| 132 | |
Elyes Haouas | 2f872e9 | 2023-07-21 07:47:00 +0200 | [diff] [blame] | 133 | if SOC_INTEL_METEORLAKE |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 134 | |
Subrata Banik | 8e15859 | 2022-12-13 12:16:52 +0530 | [diff] [blame] | 135 | config SOC_INTEL_METEORLAKE_TCSS_USB4_SUPPORT |
| 136 | bool |
| 137 | default y |
| 138 | select SOC_INTEL_COMMON_BLOCK_TCSS |
| 139 | select SOC_INTEL_COMMON_BLOCK_USB4 |
| 140 | select SOC_INTEL_COMMON_BLOCK_USB4_PCIE |
| 141 | select SOC_INTEL_COMMON_BLOCK_USB4_XHCI |
| 142 | |
Subrata Banik | 4300421 | 2022-12-13 12:20:47 +0530 | [diff] [blame] | 143 | config METEORLAKE_CAR_ENHANCED_NEM |
| 144 | bool |
| 145 | default y if !INTEL_CAR_NEM |
| 146 | select INTEL_CAR_NEM_ENHANCED |
| 147 | select CAR_HAS_SF_MASKS |
| 148 | select COS_MAPPED_TO_MSB |
| 149 | select CAR_HAS_L3_PROTECTED_WAYS |
| 150 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 151 | config MAX_CPUS |
| 152 | int |
| 153 | default 22 |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 154 | |
| 155 | config DCACHE_RAM_BASE |
| 156 | default 0xfef00000 |
| 157 | |
| 158 | config DCACHE_RAM_SIZE |
| 159 | default 0xc0000 |
| 160 | help |
| 161 | The size of the cache-as-ram region required during bootblock |
| 162 | and/or romstage. |
| 163 | |
| 164 | config DCACHE_BSP_STACK_SIZE |
| 165 | hex |
| 166 | default 0x80400 |
| 167 | help |
| 168 | The amount of anticipated stack usage in CAR by bootblock and |
| 169 | other stages. In the case of FSP_USES_CB_STACK default value will be |
| 170 | sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement |
| 171 | (~1KiB). |
| 172 | |
| 173 | config FSP_TEMP_RAM_SIZE |
| 174 | hex |
| 175 | default 0x20000 |
| 176 | help |
| 177 | The amount of anticipated heap usage in CAR by FSP. |
| 178 | Refer to Platform FSP integration guide document to know |
| 179 | the exact FSP requirement for Heap setup. |
| 180 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 181 | config CHIPSET_DEVICETREE |
| 182 | string |
| 183 | default "soc/intel/meteorlake/chipset.cb" |
| 184 | |
| 185 | config EXT_BIOS_WIN_BASE |
| 186 | default 0xf8000000 |
| 187 | |
| 188 | config EXT_BIOS_WIN_SIZE |
| 189 | default 0x2000000 |
| 190 | |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 191 | config IFD_CHIPSET |
| 192 | string |
Subrata Banik | d624e74 | 2022-07-06 06:45:57 +0000 | [diff] [blame] | 193 | default "mtl" |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 194 | |
| 195 | config IED_REGION_SIZE |
| 196 | hex |
| 197 | default 0x400000 |
| 198 | |
| 199 | config HEAP_SIZE |
| 200 | hex |
Subrata Banik | 71a2a3d | 2023-08-03 10:26:21 +0000 | [diff] [blame] | 201 | default 0x80000 if BMP_LOGO |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 202 | default 0x10000 |
| 203 | |
Subrata Banik | a33bcb9 | 2022-07-06 07:07:26 +0000 | [diff] [blame] | 204 | # Intel recommends reserving the PCIe TBT root port resources as below: |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 205 | # - 42 buses |
| 206 | # - 194 MiB Non-prefetchable memory |
| 207 | # - 448 MiB Prefetchable memory |
| 208 | if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES |
| 209 | |
| 210 | config PCIEXP_HOTPLUG_BUSES |
| 211 | int |
| 212 | default 42 |
| 213 | |
| 214 | config PCIEXP_HOTPLUG_MEM |
| 215 | hex |
| 216 | default 0xc200000 |
| 217 | |
| 218 | config PCIEXP_HOTPLUG_PREFETCH_MEM |
| 219 | hex |
| 220 | default 0x1c000000 |
| 221 | |
| 222 | endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES |
| 223 | |
| 224 | config MAX_TBT_ROOT_PORTS |
| 225 | int |
| 226 | default 4 |
| 227 | |
| 228 | config MAX_ROOT_PORTS |
| 229 | int |
| 230 | default 12 |
| 231 | |
| 232 | config MAX_PCIE_CLOCK_SRC |
| 233 | int |
| 234 | default 9 |
| 235 | |
| 236 | config SMM_TSEG_SIZE |
| 237 | hex |
| 238 | default 0x800000 |
| 239 | |
| 240 | config SMM_RESERVED_SIZE |
| 241 | hex |
| 242 | default 0x200000 |
| 243 | |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 244 | config PCR_BASE_ADDRESS |
| 245 | hex |
| 246 | default 0xe0000000 |
| 247 | help |
| 248 | This option allows you to select MMIO Base Address of sideband bus. |
| 249 | |
Subrata Banik | 5557fbe | 2023-07-12 14:31:09 +0530 | [diff] [blame] | 250 | config IOE_PCR_BASE_ADDRESS |
| 251 | hex |
| 252 | default 0x3fff0000000 |
| 253 | help |
| 254 | This option allows you to select MMIO Base Address of IOE sideband bus. |
| 255 | |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 256 | config ECAM_MMCONF_BASE_ADDRESS |
| 257 | default 0xc0000000 |
| 258 | |
Sridhar Siricilla | d9c8269 | 2023-01-05 17:08:17 +0530 | [diff] [blame] | 259 | config SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR |
| 260 | int |
| 261 | default 125 |
| 262 | |
| 263 | config SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR |
| 264 | int |
| 265 | default 100 |
| 266 | |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 267 | config CPU_BCLK_MHZ |
| 268 | int |
| 269 | default 100 |
| 270 | |
| 271 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| 272 | int |
| 273 | default 120 |
| 274 | |
| 275 | config CPU_XTAL_HZ |
| 276 | default 38400000 |
| 277 | |
| 278 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 279 | int |
| 280 | default 133 |
| 281 | |
| 282 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 283 | int |
Subrata Banik | e54a8fd | 2022-07-06 12:54:48 +0000 | [diff] [blame] | 284 | default 3 |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 285 | |
| 286 | config SOC_INTEL_I2C_DEV_MAX |
| 287 | int |
| 288 | default 6 |
| 289 | |
| 290 | config SOC_INTEL_UART_DEV_MAX |
| 291 | int |
| 292 | default 3 |
| 293 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 294 | config SOC_INTEL_USB2_DEV_MAX |
| 295 | int |
| 296 | default 10 |
| 297 | |
| 298 | config SOC_INTEL_USB3_DEV_MAX |
| 299 | int |
| 300 | default 2 |
| 301 | |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 302 | config CONSOLE_UART_BASE_ADDRESS |
| 303 | hex |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 304 | default 0xfe02c000 |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 305 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 306 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 307 | config VBT_DATA_SIZE_KB |
| 308 | int |
| 309 | default 9 |
| 310 | |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 311 | # Clock divider parameters for 115200 baud rate |
Angel Pons | 054ff5e | 2022-06-26 10:19:53 +0200 | [diff] [blame] | 312 | # Baudrate = (UART source clock * M) /(N *16) |
Wonkyu Kim | 60d9b89 | 2022-10-10 23:01:38 -0700 | [diff] [blame] | 313 | # MTL UART source clock: 100MHz |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 314 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 315 | hex |
| 316 | default 0x25a |
| 317 | |
| 318 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 319 | hex |
| 320 | default 0x7fff |
| 321 | |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 322 | config VBOOT |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 323 | select VBOOT_SEPARATE_VERSTAGE |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 324 | select VBOOT_MUST_REQUEST_DISPLAY |
| 325 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 326 | select VBOOT_VBNV_CMOS |
| 327 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 328 | select VBOOT_X86_SHA256_ACCELERATION |
| 329 | |
Subrata Banik | febd3d7 | 2022-05-30 13:59:25 +0530 | [diff] [blame] | 330 | # Default hash block size is 1KiB. Increasing it to 4KiB to improve |
| 331 | # hashing time as well as read time. |
| 332 | config VBOOT_HASH_BLOCK_SIZE |
| 333 | hex |
| 334 | default 0x1000 |
| 335 | |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 336 | config CBFS_SIZE |
| 337 | hex |
| 338 | default 0x200000 |
| 339 | |
| 340 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 341 | hex |
Subrata Banik | 7d1995c | 2022-05-30 13:56:13 +0530 | [diff] [blame] | 342 | default 0x2000 |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 343 | |
Kapil Porwal | 1eb4425 | 2023-01-18 01:10:04 +0530 | [diff] [blame] | 344 | config CONSOLE_CBMEM_BUFFER_SIZE |
| 345 | hex |
Subrata Banik | deebd94 | 2023-05-08 10:29:42 +0000 | [diff] [blame] | 346 | default 0x100000 if BUILDING_WITH_DEBUG_FSP |
Kapil Porwal | 1eb4425 | 2023-01-18 01:10:04 +0530 | [diff] [blame] | 347 | default 0x40000 |
| 348 | |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 349 | config FSP_HEADER_PATH |
| 350 | string "Location of FSP headers" |
| 351 | default "src/vendorcode/intel/fsp/fsp2_0/meteorlake/" |
| 352 | |
| 353 | config FSP_FD_PATH |
| 354 | string |
| 355 | depends on FSP_USE_REPO |
| 356 | default "3rdparty/fsp/MeteorLakeFspBinPkg/Fsp.fd" |
| 357 | |
| 358 | config SOC_INTEL_METEORLAKE_DEBUG_CONSENT |
| 359 | int "Debug Consent for MTL" |
Kane Chen | 2d8bc34 | 2023-08-02 15:29:21 +0800 | [diff] [blame] | 360 | # USB DBC is more common for developers so make this default to 6 if |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 361 | # SOC_INTEL_DEBUG_CONSENT=y |
Kane Chen | 2d8bc34 | 2023-08-02 15:29:21 +0800 | [diff] [blame] | 362 | default 6 if SOC_INTEL_DEBUG_CONSENT |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 363 | default 0 |
| 364 | help |
| 365 | This is to control debug interface on SOC. |
| 366 | Setting non-zero value will allow to use DBC or DCI to debug SOC. |
| 367 | PlatformDebugConsent in FspmUpd.h has the details. |
| 368 | |
| 369 | Desired platform debug type are |
Kane Chen | 2d8bc34 | 2023-08-02 15:29:21 +0800 | [diff] [blame] | 370 | 0:Disabled, 2:Enabled Trace Active, 4:Enabled Trace Ready, |
| 371 | 6:Enable Trace Power-Off, 7:Manual |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 372 | |
| 373 | config DATA_BUS_WIDTH |
| 374 | int |
| 375 | default 128 |
| 376 | |
| 377 | config DIMMS_PER_CHANNEL |
| 378 | int |
| 379 | default 2 |
| 380 | |
| 381 | config MRC_CHANNEL_WIDTH |
| 382 | int |
| 383 | default 16 |
| 384 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame] | 385 | config SOC_INTEL_GFX_FRAMEBUFFER_OFFSET |
| 386 | hex |
| 387 | default 0x800000 |
| 388 | |
Kapil Porwal | e988cc2 | 2023-01-16 16:41:49 +0000 | [diff] [blame] | 389 | config FSP_PUBLISH_MBP_HOB |
| 390 | bool |
| 391 | default n if CHROMEOS |
| 392 | default y |
| 393 | help |
| 394 | This is to control creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. |
| 395 | Disabling it for the platforms, which do not use MBP HOB, can improve the boot time. |
| 396 | |
Subrata Banik | 6ee454a | 2023-03-30 21:01:44 +0530 | [diff] [blame] | 397 | config BUILDING_WITH_DEBUG_FSP |
| 398 | bool "Debug FSP is used for the build" |
| 399 | default n |
| 400 | help |
| 401 | Set this option if debug build of FSP is used. |
| 402 | |
Subrata Banik | fa85b0f | 2023-04-02 15:31:06 +0530 | [diff] [blame] | 403 | config DROP_CPU_FEATURE_PROGRAM_IN_FSP |
| 404 | bool |
Subrata Banik | 03ff5db | 2023-04-02 15:44:13 +0530 | [diff] [blame] | 405 | default y if MP_SERVICES_PPI_V2_NOOP || CHROMEOS |
Subrata Banik | fa85b0f | 2023-04-02 15:31:06 +0530 | [diff] [blame] | 406 | default n |
| 407 | help |
| 408 | This is to avoid FSP running basic CPU feature programming on BSP |
| 409 | and on APs using the "CpuFeaturesPei.efi" module. The feature programming |
| 410 | includes enabling x2APIC, MCA, MCE and Turbo etc. |
| 411 | |
| 412 | Most of these feature programming are getting performed today in scope |
| 413 | of coreboot doing MP Init. Running these redundant programming in scope |
| 414 | of FSP (when `USE_FSP_FEATURE_PROGRAM_ON_APS` config is enabled) would |
| 415 | results in CPU exception. |
| 416 | |
| 417 | SoC users to select this config after dropping "CpuFeaturesPei.ffs" module |
| 418 | from FSP-S Firmware Volume (FV). Upon selection, coreboot runs those additional |
| 419 | feature programming on BSP and APs. |
| 420 | |
| 421 | This feature is default enabled, in case of "coreboot running MP init" |
| 422 | aka MP_SERVICES_PPI_V2_NOOP config is selected. |
| 423 | |
Ravi Sarawadi | 31e0aeb | 2022-10-12 00:05:41 -0700 | [diff] [blame] | 424 | config PCIE_LTR_MAX_SNOOP_LATENCY |
| 425 | hex |
| 426 | default 0x100f |
| 427 | help |
| 428 | Latency tolerance reporting, max snoop latency value defaults to 15.73 ms. |
| 429 | |
| 430 | config PCIE_LTR_MAX_NO_SNOOP_LATENCY |
| 431 | hex |
| 432 | default 0x100f |
| 433 | help |
| 434 | Latency tolerance reporting, max non-snoop latency value defaults to 15.73 ms. |
| 435 | |
Kane Chen | 70c6fb4 | 2023-07-12 19:11:41 +0800 | [diff] [blame] | 436 | config IOE_DIE_CLOCK_START |
| 437 | int |
| 438 | default 6 if SOC_INTEL_METEORLAKE_U_H |
| 439 | |
Subrata Banik | 36d612c | 2023-08-04 23:43:53 +0530 | [diff] [blame] | 440 | config HAVE_BMP_LOGO_COMPRESS_LZMA |
| 441 | default n |
| 442 | |
Krishna Prasad Bhat | 1830927 | 2023-09-21 23:54:53 +0530 | [diff] [blame] | 443 | # The default offset to store CSE RW FW version information is at 68. |
| 444 | # However, in Intel Meteor Lake based systems that use PSR, the additional |
| 445 | # size required to keep CSE RW FW version information and PSR back-up status |
| 446 | # in adjacent CMOS memory at offset 68 is not available. Therefore, we |
| 447 | # override the default offset to 161, which has enough space to keep both |
| 448 | # the CSE related information together. |
| 449 | config SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET |
| 450 | int |
| 451 | default 161 |
| 452 | |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 453 | endif |