Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 1 | config SOC_INTEL_METEORLAKE |
| 2 | bool |
| 3 | |
| 4 | if SOC_INTEL_METEORLAKE |
| 5 | |
| 6 | config CPU_SPECIFIC_OPTIONS |
| 7 | def_bool y |
| 8 | select ARCH_X86 |
| 9 | select BOOT_DEVICE_SUPPORTS_WRITES |
| 10 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame^] | 11 | select CACHE_MRC_SETTINGS |
| 12 | select CPU_INTEL_COMMON |
| 13 | select FSP_M_XIP |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 14 | select IDT_IN_EVERY_STAGE |
| 15 | select INTEL_CAR_NEM |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame^] | 16 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
| 17 | select IOAPIC |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 18 | select MICROCODE_BLOB_UNDISCLOSED |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame^] | 19 | select MRC_SETTINGS_PROTECT |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 20 | select SOC_INTEL_COMMON |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame^] | 21 | select SOC_INTEL_COMMON_BLOCK |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 22 | select SOC_INTEL_COMMON_BLOCK_CAR |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame^] | 23 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 24 | select SOC_INTEL_COMMON_BLOCK_CPU |
| 25 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame^] | 26 | select SOC_INTEL_COMMON_BLOCK_MEMINIT |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 27 | select SOC_INTEL_COMMON_BLOCK_SA |
| 28 | select SOC_INTEL_COMMON_PCH_BASE |
| 29 | select SOC_INTEL_COMMON_RESET |
| 30 | select SSE2 |
| 31 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 32 | select TSC_MONOTONIC_TIMER |
| 33 | select UDELAY_TSC |
| 34 | |
| 35 | config DCACHE_RAM_BASE |
| 36 | default 0xfef00000 |
| 37 | |
| 38 | config DCACHE_RAM_SIZE |
| 39 | default 0xc0000 |
| 40 | help |
| 41 | The size of the cache-as-ram region required during bootblock |
| 42 | and/or romstage. |
| 43 | |
| 44 | config DCACHE_BSP_STACK_SIZE |
| 45 | hex |
| 46 | default 0x80400 |
| 47 | help |
| 48 | The amount of anticipated stack usage in CAR by bootblock and |
| 49 | other stages. In the case of FSP_USES_CB_STACK default value will be |
| 50 | sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement |
| 51 | (~1KiB). |
| 52 | |
| 53 | config FSP_TEMP_RAM_SIZE |
| 54 | hex |
| 55 | default 0x20000 |
| 56 | help |
| 57 | The amount of anticipated heap usage in CAR by FSP. |
| 58 | Refer to Platform FSP integration guide document to know |
| 59 | the exact FSP requirement for Heap setup. |
| 60 | |
| 61 | config IFD_CHIPSET |
| 62 | string |
| 63 | default "mtl" |
| 64 | |
| 65 | config IED_REGION_SIZE |
| 66 | hex |
| 67 | default 0x400000 |
| 68 | |
| 69 | config HEAP_SIZE |
| 70 | hex |
| 71 | default 0x10000 |
| 72 | |
| 73 | config PCR_BASE_ADDRESS |
| 74 | hex |
| 75 | default 0xe0000000 |
| 76 | help |
| 77 | This option allows you to select MMIO Base Address of sideband bus. |
| 78 | |
| 79 | config ECAM_MMCONF_BASE_ADDRESS |
| 80 | default 0xc0000000 |
| 81 | |
| 82 | config CPU_BCLK_MHZ |
| 83 | int |
| 84 | default 100 |
| 85 | |
| 86 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| 87 | int |
| 88 | default 120 |
| 89 | |
| 90 | config CPU_XTAL_HZ |
| 91 | default 38400000 |
| 92 | |
| 93 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 94 | int |
| 95 | default 133 |
| 96 | |
| 97 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 98 | int |
| 99 | default 2 |
| 100 | |
| 101 | config SOC_INTEL_I2C_DEV_MAX |
| 102 | int |
| 103 | default 6 |
| 104 | |
| 105 | config SOC_INTEL_UART_DEV_MAX |
| 106 | int |
| 107 | default 3 |
| 108 | |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 109 | config CONSOLE_UART_BASE_ADDRESS |
| 110 | hex |
| 111 | default 0xfe03e000 |
| 112 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 113 | |
| 114 | # Clock divider parameters for 115200 baud rate |
Angel Pons | 054ff5e | 2022-06-26 10:19:53 +0200 | [diff] [blame] | 115 | # Baudrate = (UART source clock * M) /(N *16) |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 116 | # MTL UART source clock: 120MHz |
| 117 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 118 | hex |
| 119 | default 0x25a |
| 120 | |
| 121 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 122 | hex |
| 123 | default 0x7fff |
| 124 | |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame^] | 125 | config VBOOT |
| 126 | select VBOOT_MUST_REQUEST_DISPLAY |
| 127 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 128 | select VBOOT_VBNV_CMOS |
| 129 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 130 | select VBOOT_X86_SHA256_ACCELERATION |
| 131 | |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 132 | config CBFS_SIZE |
| 133 | hex |
| 134 | default 0x200000 |
| 135 | |
| 136 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 137 | hex |
Subrata Banik | ea4f8c2 | 2022-05-30 13:56:13 +0530 | [diff] [blame] | 138 | default 0x2000 |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 139 | |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame^] | 140 | config FSP_HEADER_PATH |
| 141 | string "Location of FSP headers" |
| 142 | default "src/vendorcode/intel/fsp/fsp2_0/meteorlake/" |
| 143 | |
| 144 | config FSP_FD_PATH |
| 145 | string |
| 146 | depends on FSP_USE_REPO |
| 147 | default "3rdparty/fsp/MeteorLakeFspBinPkg/Fsp.fd" |
| 148 | |
| 149 | config SOC_INTEL_METEORLAKE_DEBUG_CONSENT |
| 150 | int "Debug Consent for MTL" |
| 151 | # USB DBC is more common for developers so make this default to 3 if |
| 152 | # SOC_INTEL_DEBUG_CONSENT=y |
| 153 | default 3 if SOC_INTEL_DEBUG_CONSENT |
| 154 | default 0 |
| 155 | help |
| 156 | This is to control debug interface on SOC. |
| 157 | Setting non-zero value will allow to use DBC or DCI to debug SOC. |
| 158 | PlatformDebugConsent in FspmUpd.h has the details. |
| 159 | |
| 160 | Desired platform debug type are |
| 161 | 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), |
| 162 | 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), |
| 163 | 6:Enable (2-wire DCI OOB), 7:Manual |
| 164 | |
| 165 | config DATA_BUS_WIDTH |
| 166 | int |
| 167 | default 128 |
| 168 | |
| 169 | config DIMMS_PER_CHANNEL |
| 170 | int |
| 171 | default 2 |
| 172 | |
| 173 | config MRC_CHANNEL_WIDTH |
| 174 | int |
| 175 | default 16 |
| 176 | |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 177 | endif |