Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 1 | config SOC_INTEL_METEORLAKE |
| 2 | bool |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame^] | 3 | help |
| 4 | Intel Meteorlake support |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 5 | |
| 6 | if SOC_INTEL_METEORLAKE |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame^] | 10 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 11 | select ARCH_X86 |
| 12 | select BOOT_DEVICE_SUPPORTS_WRITES |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 13 | select CACHE_MRC_SETTINGS |
| 14 | select CPU_INTEL_COMMON |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame^] | 15 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
| 16 | select CPU_SUPPORTS_INTEL_TME |
| 17 | select CPU_SUPPORTS_PM_TIMER_EMULATION |
| 18 | select DRIVERS_INTEL_USB4_RETIMER |
| 19 | select FSP_COMPRESS_FSP_S_LZ4 |
| 20 | select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 21 | select FSP_M_XIP |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame^] | 22 | select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 |
| 23 | select GENERIC_GPIO_LIB |
| 24 | select HAVE_FSP_GOP |
| 25 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
| 26 | select HAVE_SMI_HANDLER |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 27 | select IDT_IN_EVERY_STAGE |
| 28 | select INTEL_CAR_NEM |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame^] | 29 | select INTEL_GMA_ACPI |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 30 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
| 31 | select IOAPIC |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame^] | 32 | select INTEL_TME |
| 33 | select USE_INTEL_FSP_MP_INIT |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 34 | select MRC_SETTINGS_PROTECT |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame^] | 35 | select PARALLEL_MP_AP_WORK |
| 36 | select MICROCODE_BLOB_UNDISCLOSED |
| 37 | select PLATFORM_USES_FSP2_3 |
| 38 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 39 | select SOC_INTEL_COMMON |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 40 | select SOC_INTEL_COMMON_BLOCK |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 41 | select SOC_INTEL_COMMON_BLOCK_CAR |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 42 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 43 | select SOC_INTEL_COMMON_BLOCK_CPU |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame^] | 44 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
| 45 | select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE |
| 46 | select SOC_INTEL_COMMON_BLOCK_DTT |
| 47 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 48 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame^] | 49 | select SOC_INTEL_COMMON_BLOCK_HDA |
| 50 | select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT |
| 51 | select SOC_INTEL_COMMON_BLOCK_IPU |
| 52 | select SOC_INTEL_COMMON_BLOCK_IOE_P2SB |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 53 | select SOC_INTEL_COMMON_BLOCK_MEMINIT |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame^] | 54 | select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 |
| 55 | select SOC_INTEL_COMMON_BLOCK_PMC_EPOC |
| 56 | select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 57 | select SOC_INTEL_COMMON_BLOCK_SA |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame^] | 58 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 59 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
| 60 | select SOC_INTEL_COMMON_BLOCK_TCSS |
| 61 | select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC |
| 62 | select SOC_INTEL_COMMON_BLOCK_USB4 |
| 63 | select SOC_INTEL_COMMON_BLOCK_USB4_PCIE |
| 64 | select SOC_INTEL_COMMON_BLOCK_USB4_XHCI |
| 65 | select SOC_INTEL_COMMON_BLOCK_XHCI |
| 66 | select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG |
| 67 | select SOC_INTEL_COMMON_BASECODE |
| 68 | select SOC_INTEL_COMMON_FSP_RESET |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 69 | select SOC_INTEL_COMMON_PCH_BASE |
| 70 | select SOC_INTEL_COMMON_RESET |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame^] | 71 | select SOC_INTEL_COMMON_BLOCK_IOC |
| 72 | select SOC_INTEL_CSE_SET_EOP |
| 73 | select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 74 | select SSE2 |
| 75 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 76 | select TSC_MONOTONIC_TIMER |
| 77 | select UDELAY_TSC |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame^] | 78 | select UDK_202111_BINDING |
| 79 | select DISPLAY_FSP_VERSION_INFO |
| 80 | |
| 81 | config MAX_CPUS |
| 82 | int |
| 83 | default 22 |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 84 | |
| 85 | config DCACHE_RAM_BASE |
| 86 | default 0xfef00000 |
| 87 | |
| 88 | config DCACHE_RAM_SIZE |
| 89 | default 0xc0000 |
| 90 | help |
| 91 | The size of the cache-as-ram region required during bootblock |
| 92 | and/or romstage. |
| 93 | |
| 94 | config DCACHE_BSP_STACK_SIZE |
| 95 | hex |
| 96 | default 0x80400 |
| 97 | help |
| 98 | The amount of anticipated stack usage in CAR by bootblock and |
| 99 | other stages. In the case of FSP_USES_CB_STACK default value will be |
| 100 | sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement |
| 101 | (~1KiB). |
| 102 | |
| 103 | config FSP_TEMP_RAM_SIZE |
| 104 | hex |
| 105 | default 0x20000 |
| 106 | help |
| 107 | The amount of anticipated heap usage in CAR by FSP. |
| 108 | Refer to Platform FSP integration guide document to know |
| 109 | the exact FSP requirement for Heap setup. |
| 110 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame^] | 111 | config CHIPSET_DEVICETREE |
| 112 | string |
| 113 | default "soc/intel/meteorlake/chipset.cb" |
| 114 | |
| 115 | config EXT_BIOS_WIN_BASE |
| 116 | default 0xf8000000 |
| 117 | |
| 118 | config EXT_BIOS_WIN_SIZE |
| 119 | default 0x2000000 |
| 120 | |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 121 | config IFD_CHIPSET |
| 122 | string |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame^] | 123 | default "ifd2" |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 124 | |
| 125 | config IED_REGION_SIZE |
| 126 | hex |
| 127 | default 0x400000 |
| 128 | |
| 129 | config HEAP_SIZE |
| 130 | hex |
| 131 | default 0x10000 |
| 132 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame^] | 133 | # Intel recommends reserving the following resources per PCIe TBT root port, |
| 134 | # from ADL BIOS Spec (doc #627270) Revision 0.6.0 Section 7.2.5.1.5 |
| 135 | # - 42 buses |
| 136 | # - 194 MiB Non-prefetchable memory |
| 137 | # - 448 MiB Prefetchable memory |
| 138 | if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES |
| 139 | |
| 140 | config PCIEXP_HOTPLUG_BUSES |
| 141 | int |
| 142 | default 42 |
| 143 | |
| 144 | config PCIEXP_HOTPLUG_MEM |
| 145 | hex |
| 146 | default 0xc200000 |
| 147 | |
| 148 | config PCIEXP_HOTPLUG_PREFETCH_MEM |
| 149 | hex |
| 150 | default 0x1c000000 |
| 151 | |
| 152 | endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES |
| 153 | |
| 154 | config MAX_TBT_ROOT_PORTS |
| 155 | int |
| 156 | default 4 |
| 157 | |
| 158 | config MAX_ROOT_PORTS |
| 159 | int |
| 160 | default 12 |
| 161 | |
| 162 | config MAX_PCIE_CLOCK_SRC |
| 163 | int |
| 164 | default 9 |
| 165 | |
| 166 | config SMM_TSEG_SIZE |
| 167 | hex |
| 168 | default 0x800000 |
| 169 | |
| 170 | config SMM_RESERVED_SIZE |
| 171 | hex |
| 172 | default 0x200000 |
| 173 | |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 174 | config PCR_BASE_ADDRESS |
| 175 | hex |
| 176 | default 0xe0000000 |
| 177 | help |
| 178 | This option allows you to select MMIO Base Address of sideband bus. |
| 179 | |
| 180 | config ECAM_MMCONF_BASE_ADDRESS |
| 181 | default 0xc0000000 |
| 182 | |
| 183 | config CPU_BCLK_MHZ |
| 184 | int |
| 185 | default 100 |
| 186 | |
| 187 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| 188 | int |
| 189 | default 120 |
| 190 | |
| 191 | config CPU_XTAL_HZ |
| 192 | default 38400000 |
| 193 | |
| 194 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 195 | int |
| 196 | default 133 |
| 197 | |
| 198 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 199 | int |
| 200 | default 2 |
| 201 | |
| 202 | config SOC_INTEL_I2C_DEV_MAX |
| 203 | int |
| 204 | default 6 |
| 205 | |
| 206 | config SOC_INTEL_UART_DEV_MAX |
| 207 | int |
| 208 | default 3 |
| 209 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame^] | 210 | config SOC_INTEL_USB2_DEV_MAX |
| 211 | int |
| 212 | default 10 |
| 213 | |
| 214 | config SOC_INTEL_USB3_DEV_MAX |
| 215 | int |
| 216 | default 2 |
| 217 | |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 218 | config CONSOLE_UART_BASE_ADDRESS |
| 219 | hex |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame^] | 220 | default 0xfe02c000 |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 221 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 222 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame^] | 223 | config VBT_DATA_SIZE_KB |
| 224 | int |
| 225 | default 9 |
| 226 | |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 227 | # Clock divider parameters for 115200 baud rate |
Angel Pons | 054ff5e | 2022-06-26 10:19:53 +0200 | [diff] [blame] | 228 | # Baudrate = (UART source clock * M) /(N *16) |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 229 | # MTL UART source clock: 120MHz |
| 230 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 231 | hex |
| 232 | default 0x25a |
| 233 | |
| 234 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 235 | hex |
| 236 | default 0x7fff |
| 237 | |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 238 | config VBOOT |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame^] | 239 | select VBOOT_SEPARATE_VERSTAGE |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 240 | select VBOOT_MUST_REQUEST_DISPLAY |
| 241 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 242 | select VBOOT_VBNV_CMOS |
| 243 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 244 | select VBOOT_X86_SHA256_ACCELERATION |
| 245 | |
Subrata Banik | febd3d7 | 2022-05-30 13:59:25 +0530 | [diff] [blame] | 246 | # Default hash block size is 1KiB. Increasing it to 4KiB to improve |
| 247 | # hashing time as well as read time. |
| 248 | config VBOOT_HASH_BLOCK_SIZE |
| 249 | hex |
| 250 | default 0x1000 |
| 251 | |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 252 | config CBFS_SIZE |
| 253 | hex |
| 254 | default 0x200000 |
| 255 | |
| 256 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 257 | hex |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame^] | 258 | default 0x1400 |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 259 | |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 260 | config FSP_HEADER_PATH |
| 261 | string "Location of FSP headers" |
| 262 | default "src/vendorcode/intel/fsp/fsp2_0/meteorlake/" |
| 263 | |
| 264 | config FSP_FD_PATH |
| 265 | string |
| 266 | depends on FSP_USE_REPO |
| 267 | default "3rdparty/fsp/MeteorLakeFspBinPkg/Fsp.fd" |
| 268 | |
| 269 | config SOC_INTEL_METEORLAKE_DEBUG_CONSENT |
| 270 | int "Debug Consent for MTL" |
| 271 | # USB DBC is more common for developers so make this default to 3 if |
| 272 | # SOC_INTEL_DEBUG_CONSENT=y |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame^] | 273 | default 5 if SOC_INTEL_DEBUG_CONSENT |
Ravi Sarawadi | 8069b5d | 2022-04-10 23:36:52 -0700 | [diff] [blame] | 274 | default 0 |
| 275 | help |
| 276 | This is to control debug interface on SOC. |
| 277 | Setting non-zero value will allow to use DBC or DCI to debug SOC. |
| 278 | PlatformDebugConsent in FspmUpd.h has the details. |
| 279 | |
| 280 | Desired platform debug type are |
| 281 | 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), |
| 282 | 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), |
| 283 | 6:Enable (2-wire DCI OOB), 7:Manual |
| 284 | |
| 285 | config DATA_BUS_WIDTH |
| 286 | int |
| 287 | default 128 |
| 288 | |
| 289 | config DIMMS_PER_CHANNEL |
| 290 | int |
| 291 | default 2 |
| 292 | |
| 293 | config MRC_CHANNEL_WIDTH |
| 294 | int |
| 295 | default 16 |
| 296 | |
Ravi Sarawadi | 91ffac8 | 2022-05-07 16:37:09 -0700 | [diff] [blame^] | 297 | config SOC_INTEL_GFX_FRAMEBUFFER_OFFSET |
| 298 | hex |
| 299 | default 0x800000 |
| 300 | |
Ravi Sarawadi | b8224f4 | 2022-04-10 23:31:24 -0700 | [diff] [blame] | 301 | endif |