soc/intel/meteorlake: Add entry for GSPI2 device
This patch adds GSPI2 (PCI device B0:D18:F6) entry into the chipset.cb.
Additionally, increases `CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX` value
to include GSPI2 as well.
BUG=b:224325352
TEST=Able to build and boot Google/Rex platform.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I901128a1773fc6d2ba87e3e4972f45ad4a754d35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65675
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index c70e472..b2a094f 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -208,7 +208,7 @@
config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
int
- default 2
+ default 3
config SOC_INTEL_I2C_DEV_MAX
int