| commit | e96993db6990a2693fe231adb1ec200a7efc6d51 | [log] [tgz] |
|---|---|---|
| author | Subrata Banik <subratabanik@google.com> | Sat Jul 09 22:06:45 2022 +0000 |
| committer | Felix Held <felix-coreboot@felixheld.de> | Mon Jul 18 15:42:30 2022 +0000 |
| tree | 3b0c4130f4a7f043e6e973fb08abd0b4d62e70e1 | |
| parent | f6d725c0d3694536ca55c93f1437f825e9fd7b52 [diff] |
soc/intel/meteorlake: Enable `DEFAULT_X2APIC_LATE_WORKAROUND` This patch ensures Intel Meteor Lake can enable the X2APIC feature. While debugging Intel Meteor Lake (MTL) based platforms it seems like enabling `DEFAULT_X2APIC` runs into a hang while coreboot tries to bring the application processors (APs) from reset using X2APIC mode. [INFO ] LAPIC 0x10 switched to X2APIC mode. ... [DEBUG] Attempting to start 3 APs [DEBUG] Waiting for 10ms after sending INIT. [DEBUG] Waiting for SIPI to complete... [DEBUG] done. [DEBUG] Waiting for SIPI to complete... [DEBUG] done. [ERROR] Not all APs checked in: 0/3. [DEBUG] 0/3 eventually checked in? [ERROR] MP initialization failure. [ERROR] MP initialization failure. Note: The AP bring up flow between XAPIC and X2APIC are the same except the way to access those LAPIC registers. X2APIC expects to access all LAPIC registers using MSR (base with 0x800). The correct flow to enable X2APIC on MTL would be as follows: 1. Let BSP bring all APs in XAPIC mode. [INFO ] LAPIC 0x10 in XAPIC mode. ... [DEBUG] Attempting to start 3 APs [DEBUG] Waiting for 10ms after sending INIT. [DEBUG] Waiting for SIPI to complete... [DEBUG] done. [DEBUG] Waiting for SIPI to complete... [DEBUG] done. [INFO ] LAPIC 0x11 in XAPIC mode. [INFO ] LAPIC 0x0 in XAPIC mode. [INFO ] LAPIC 0x80 in XAPIC mode. 2. Call enable_x2apic() function on all CPUs (BSP and APs) And at the end of #2 above, all cores will now switch to X2APIC from XAPIC. [INFO ] Initializing CPU #0 [DEBUG] CPU: vendor Intel device a06a0 [DEBUG] Clearing out pending MCEs [INFO ] LAPIC 0x10 switched to X2APIC mode. ... [INFO ] CPU #0 initialized [INFO ] Initializing CPU #1 [DEBUG] CPU: vendor Intel device a06a0 [DEBUG] Clearing out pending MCEs [INFO ] LAPIC 0x11 switched to X2APIC mode. Note: Intel MTL FSP also follow the same steps for x2APIC enablement while coreboot selects USE_INTEL_FSP_MP_INIT config instead MP_SERVICES_PPI_V2. BUG=b:219061518, b:219053812 TEST=Able to perform coreboot doing AP init with DEFAULT_X2APIC_LATE_WORKAROUND config enabled without running into any hang issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie9c8fad6c46b15b5b08c9cc4ef53f2a6872bd0ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/65741 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig and make nconfig)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.