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review.coreboot.org / coreboot / 53490444f72605f53c81e3bdbf479d1013a2d617 / . / src / soc / intel / skylake / Kconfig
blob: 5fc2a2d2403bf789dd619abb5ca89efe9274182a [file] [log] [blame]
Arthur Heymans4c7979a2019-06-17 14:30:10 +0200[diff] [blame]1config SOC_INTEL_COMMON_SKYLAKE_BASE
2 bool
3
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]4config SOC_INTEL_SKYLAKE
5 bool
Arthur Heymans4c7979a2019-06-17 14:30:10 +0200[diff] [blame]6 select SOC_INTEL_COMMON_SKYLAKE_BASE
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]7 help
8 Intel Skylake support
9
Rizwan Qureshi0700dca2017-02-09 15:57:45 +0530[diff] [blame]10config SOC_INTEL_KABYLAKE
11 bool
Arthur Heymans4c7979a2019-06-17 14:30:10 +0200[diff] [blame]12 select SOC_INTEL_COMMON_SKYLAKE_BASE
Rizwan Qureshi0700dca2017-02-09 15:57:45 +0530[diff] [blame]13 help
14 Intel Kabylake support
15
Arthur Heymans4c7979a2019-06-17 14:30:10 +0200[diff] [blame]16if SOC_INTEL_COMMON_SKYLAKE_BASE
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]17
18config CPU_SPECIFIC_OPTIONS
19 def_bool y
Aaron Durbine0a49142016-07-13 23:20:51 -0500[diff] [blame]20 select ACPI_INTEL_HARDWARE_SLEEP_VALUES
Vadim Bendebury5542bb62018-02-05 19:59:09 -0800[diff] [blame]21 select ACPI_NHLT
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]22 select ARCH_BOOTBLOCK_X86_32
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]23 select ARCH_RAMSTAGE_X86_32
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]24 select ARCH_ROMSTAGE_X86_32
25 select ARCH_VERSTAGE_X86_32
Aaron Durbine4cc8cd2016-08-11 23:55:39 -0500[diff] [blame]26 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
Aaron Durbine8e118d2016-08-12 15:00:10 -0500[diff] [blame]27 select BOOT_DEVICE_SUPPORTS_WRITES
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]28 select CACHE_MRC_SETTINGS
Duncan Laurie135c2c42016-10-17 19:47:51 -0700[diff] [blame]29 select COMMON_FADT
Nico Huber6275e342018-11-21 00:11:35 +0100[diff] [blame]30 select CPU_INTEL_COMMON
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]31 select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
Michael Niewöhner7bdedcd2019-09-01 16:49:09 +0200[diff] [blame]32 select CPU_INTEL_COMMON_HYPERTHREADING
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]33 select FSP_M_XIP
Aaron Durbinffdf9012015-07-24 13:00:36 -0500[diff] [blame]34 select GENERIC_GPIO_LIB
Vadim Bendebury5542bb62018-02-05 19:59:09 -0800[diff] [blame]35 select HAVE_FSP_GOP
Stefan Tauneref8b9572018-09-06 00:34:28 +0200[diff] [blame]36 select INTEL_DESCRIPTOR_MODE_CAPABLE
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]37 select HAVE_SMI_HANDLER
Nico Huber2f1ef982018-11-07 16:24:50 +0100[diff] [blame]38 select INTEL_CAR_NEM_ENHANCED
Patrick Rudolphc7edf182017-09-26 19:34:35 +0200[diff] [blame]39 select INTEL_GMA_ACPI
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]40 select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]41 select IOAPIC
Duncan Laurie205ed2d2016-06-02 15:23:42 -0700[diff] [blame]42 select MRC_SETTINGS_PROTECT
Vadim Bendebury5542bb62018-02-05 19:59:09 -0800[diff] [blame]43 select NO_FIXED_XIP_ROM_SIZE
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]44 select PARALLEL_MP
Furquan Shaikha5853582017-05-06 12:40:15 -0700[diff] [blame]45 select PARALLEL_MP_AP_WORK
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]46 select PLATFORM_USES_FSP2_0
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]47 select REG_SCRIPT
Subrata Banik46a71782017-06-02 18:52:24 +0530[diff] [blame]48 select SA_ENABLE_DPR
Vadim Bendebury5542bb62018-02-05 19:59:09 -0800[diff] [blame]49 select SMP
Julien Viard de Galbert2912e8e2018-08-14 16:15:26 +0200[diff] [blame]50 select PMC_GLOBAL_RESET_ENABLE_LOCK
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]51 select SOC_INTEL_COMMON
Duncan Lauriea1c8b34d2015-09-08 16:12:44 -0700[diff] [blame]52 select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
Subrata Banike074d622017-02-16 16:16:37 +0530[diff] [blame]53 select SOC_INTEL_COMMON_BLOCK
Nico Huber2f1ef982018-11-07 16:24:50 +0100[diff] [blame]54 select SOC_INTEL_COMMON_BLOCK_CAR
Subrata Banikc4986eb2018-05-09 14:55:09 +0530[diff] [blame]55 select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
Barnali Sarkar0a203d12017-05-04 18:02:17 +0530[diff] [blame]56 select SOC_INTEL_COMMON_BLOCK_CPU
Barnali Sarkar73273862017-06-13 20:22:33 +0530[diff] [blame]57 select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
Furquan Shaikh2c368892018-10-18 16:22:37 -0700[diff] [blame]58 select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
Hannah Williams1760cd32017-04-06 20:54:11 -0700[diff] [blame]59 select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS
Vadim Bendebury5542bb62018-02-05 19:59:09 -0800[diff] [blame]60 select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
Furquan Shaikh05a6f292017-03-31 14:02:47 -0700[diff] [blame]61 select SOC_INTEL_COMMON_BLOCK_GSPI
Furquan Shaikh31bff012018-09-29 23:31:04 -0700[diff] [blame]62 select SOC_INTEL_COMMON_BLOCK_HDA
Subrata Banik93ebe492017-03-14 18:24:47 +0530[diff] [blame]63 select SOC_INTEL_COMMON_BLOCK_SA
Pratik Prajapatia04aa3d2017-06-12 23:02:36 -0700[diff] [blame]64 select SOC_INTEL_COMMON_BLOCK_SGX
Michael Niewöhnerc169a472019-10-31 19:01:23 +0100[diff] [blame]65 select SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY
Subrata Banikece173c2017-12-14 18:18:34 +0530[diff] [blame]66 select SOC_INTEL_COMMON_BLOCK_SMM
67 select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
Subrata Banikafa07f72018-05-24 12:21:06 +0530[diff] [blame]68 select SOC_INTEL_COMMON_BLOCK_UART
Karthikeyan Ramasubramaniancc7cdb12019-03-20 11:38:01 -0600[diff] [blame]69 select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
Subrata Banikf513ceb2018-05-17 15:57:43 +0530[diff] [blame]70 select SOC_INTEL_COMMON_PCH_BASE
Aaron Durbinc14a1a92016-06-28 15:41:07 -0500[diff] [blame]71 select SOC_INTEL_COMMON_NHLT
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]72 select SOC_INTEL_COMMON_RESET
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]73 select SSE2
74 select SUPPORT_CPU_UCODE_IN_CBFS
Aamir Bohra842776e2017-05-25 14:12:01 +0530[diff] [blame]75 select TSC_MONOTONIC_TIMER
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]76 select TSC_SYNC_MFENCE
77 select UDELAY_TSC
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]78 select UDK_2015_BINDING
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]79
Patrick Rudolph203061c2019-09-02 09:35:21 +0200[diff] [blame]80config FSP_HYPERTHREADING
81 bool "Enable Hyper-Threading"
Patrick Rudolph203061c2019-09-02 09:35:21 +0200[diff] [blame]82 default y
83
Arthur Heymans27d3f712018-01-05 17:51:46 +0100[diff] [blame]84config CPU_INTEL_NUM_FIT_ENTRIES
85 int
86 default 10
87
Furquan Shaikh610a33a2016-07-22 16:17:53 -0700[diff] [blame]88config CHROMEOS
89 select CHROMEOS_RAMOOPS_DYNAMIC
Julius Werner58c39382017-02-13 17:53:29 -0800[diff] [blame]90
91config VBOOT
Julius Werner58c39382017-02-13 17:53:29 -0800[diff] [blame]92 select VBOOT_SEPARATE_VERSTAGE
Joel Kitching6672bd82019-04-10 16:06:21 +0800[diff] [blame]93 select VBOOT_MUST_REQUEST_DISPLAY
Furquan Shaikhb8257df2016-07-22 09:20:56 -0700[diff] [blame]94 select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
Aaron Durbina6914d22016-08-24 08:49:29 -0500[diff] [blame]95 select VBOOT_STARTS_IN_BOOTBLOCK
Furquan Shaikh2a12e2e2016-07-25 11:48:03 -0700[diff] [blame]96 select VBOOT_VBNV_CMOS
97 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
Furquan Shaikh610a33a2016-07-22 16:17:53 -0700[diff] [blame]98
Martin Roth59ff3402016-02-09 09:06:46 -0700[diff] [blame]99config CBFS_SIZE
100 hex
101 default 0x200000
102
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]103config DCACHE_RAM_BASE
Arthur Heymans432ac612017-06-13 14:17:05 +0200[diff] [blame]104 hex
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]105 default 0xfef00000
106
107config DCACHE_RAM_SIZE
Arthur Heymans432ac612017-06-13 14:17:05 +0200[diff] [blame]108 hex
Rizwan Qureshi3ad63562016-08-14 15:48:33 +0530[diff] [blame]109 default 0x40000
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]110 help
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]111 The size of the cache-as-ram region required during bootblock
112 and/or romstage.
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]113
Subrata Banik68d5d8b2016-07-18 14:13:52 +0530[diff] [blame]114config DCACHE_BSP_STACK_SIZE
115 hex
116 default 0x4000
117 help
118 The amount of anticipated stack usage in CAR by bootblock and
119 other stages.
120
121config C_ENV_BOOTBLOCK_SIZE
122 hex
Furquan Shaikh70385962016-08-24 10:28:30 -0700[diff] [blame]123 default 0xC000
Subrata Banik68d5d8b2016-07-18 14:13:52 +0530[diff] [blame]124
Subrata Banik086730b2015-12-02 11:42:04 +0530[diff] [blame]125config EXCLUDE_NATIVE_SD_INTERFACE
126 bool
127 default n
128 help
129 If you set this option to n, will not use native SD controller.
130
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]131config HEAP_SIZE
132 hex
133 default 0x80000
134
135config IED_REGION_SIZE
136 hex
137 default 0x400000
138
Subrata Banike7ceae72017-03-08 17:59:40 +0530[diff] [blame]139config PCR_BASE_ADDRESS
140 hex
141 default 0xfd000000
142 help
143 This option allows you to select MMIO Base Address of sideband bus.
144
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]145config SMM_RESERVED_SIZE
146 hex
147 default 0x200000
148
149config SMM_TSEG_SIZE
150 hex
151 default 0x800000
152
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]153config VGA_BIOS_ID
154 string
155 default "8086,0406"
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]156
Teo Boon Tiong2fc06c82016-09-15 11:11:45 +0800[diff] [blame]157config SKYLAKE_SOC_PCH_H
158 bool
159 default n
160 help
161 Choose this option if you have a PCH-H chipset.
162
Aaron Durbined8a7232015-11-24 12:35:06 -0600[diff] [blame]163config NHLT_DMIC_2CH
164 bool
165 default n
166 help
167 Include DSP firmware settings for 2 channel DMIC array.
168
169config NHLT_DMIC_4CH
170 bool
171 default n
172 help
173 Include DSP firmware settings for 4 channel DMIC array.
174
175config NHLT_NAU88L25
176 bool
177 default n
178 help
179 Include DSP firmware settings for nau88l25 headset codec.
180
181config NHLT_MAX98357
182 bool
183 default n
184 help
185 Include DSP firmware settings for max98357 amplifier.
186
Duncan Lauriee6c8a382018-03-26 02:45:02 -0700[diff] [blame]187config NHLT_MAX98373
188 bool
189 default n
190 help
191 Include DSP firmware settings for max98373 amplifier.
192
Aaron Durbined8a7232015-11-24 12:35:06 -0600[diff] [blame]193config NHLT_SSM4567
194 bool
195 default n
196 help
197 Include DSP firmware settings for ssm4567 smart amplifier.
198
Duncan Laurie4a75a662017-03-02 10:13:51 -0800[diff] [blame]199config NHLT_RT5514
200 bool
201 default n
202 help
203 Include DSP firmware settings for rt5514 DSP.
204
Rizwan Qureshi17335fa2017-01-14 06:08:21 +0530[diff] [blame]205config NHLT_RT5663
206 bool
207 default n
208 help
209 Include DSP firmware settings for rt5663 headset codec.
210
211config NHLT_MAX98927
212 bool
213 default n
214 help
215 Include DSP firmware settings for max98927 amplifier.
216
Naveen Manohar83670c52017-11-04 02:55:09 +0530[diff] [blame]217config NHLT_DA7219
218 bool
219 default n
220 help
221 Include DSP firmware settings for DA7219 headset codec.
222
Patrick Georgi6539e102018-09-13 11:48:43 -0400[diff] [blame]223config FSP_HEADER_PATH
Patrick Georgic6382cd2018-10-26 22:03:17 +0200[diff] [blame]224 string "Location of FSP headers"
Patrick Georgi6539e102018-09-13 11:48:43 -0400[diff] [blame]225 # Use KabylakeFsp for both Skylake and Kabylake as it supports both.
226 # SkylakeFsp is FSP 1.1 and therefore incompatible.
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]227 default "3rdparty/fsp/KabylakeFspBinPkg/Include/"
Patrick Georgi6539e102018-09-13 11:48:43 -0400[diff] [blame]228
229config FSP_FD_PATH
230 string
231 depends on FSP_USE_REPO
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]232 default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
Patrick Georgi6539e102018-09-13 11:48:43 -0400[diff] [blame]233
Aaron Durbine56191e2016-08-11 09:50:49 -0500[diff] [blame]234config SPI_FLASH_INCLUDE_ALL_DRIVERS
235 bool
236 default n
237
Rizwan Qureshid8bb69a2016-11-08 21:01:09 +0530[diff] [blame]238config MAX_ROOT_PORTS
239 int
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]240 default 24
Rizwan Qureshid8bb69a2016-11-08 21:01:09 +0530[diff] [blame]241
Jenny TC2864f852017-02-09 16:01:59 +0530[diff] [blame]242config NO_FADT_8042
243 bool
244 default n
245 help
246 Choose this option if you want to disable 8042 Keyboard
247
Aaron Durbin551e4be2018-04-10 09:24:54 -0600[diff] [blame]248config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
Furquan Shaikh340908a2017-04-04 11:47:19 -0700[diff] [blame]249 int
250 default 120
251
Chris Chingb8dc63b2017-12-06 14:26:15 -0700[diff] [blame]252config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
253 int
Aaron Durbin551e4be2018-04-10 09:24:54 -0600[diff] [blame]254 default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
Chris Chingb8dc63b2017-12-06 14:26:15 -0700[diff] [blame]255
Furquan Shaikh05a6f292017-03-31 14:02:47 -0700[diff] [blame]256config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
257 int
258 default 2
259
Subrata Banikc4986eb2018-05-09 14:55:09 +0530[diff] [blame]260config SOC_INTEL_I2C_DEV_MAX
261 int
262 default 6
263
Aamir Bohra1041d392017-06-02 11:56:14 +0530[diff] [blame]264config CPU_BCLK_MHZ
265 int
266 default 100
267
Nico Huber99954182019-05-29 23:33:06 +0200[diff] [blame]268config CONSOLE_UART_BASE_ADDRESS
269 hex
270 default 0xfe030000
271 depends on INTEL_LPSS_UART_FOR_CONSOLE
272
Furquan Shaikh3406dd62017-08-04 15:58:26 -0700[diff] [blame]273# Clock divider parameters for 115200 baud rate
274config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
275 hex
276 default 0x30
277
278config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
279 hex
280 default 0xc35
281
Furquan Shaikha3ad9902018-03-21 10:45:08 -0700[diff] [blame]282config IFD_CHIPSET
283 string
284 default "sklkbl"
285
Patrick Rudolph5fffb5e2019-07-25 11:55:30 +0200[diff] [blame]286config INTEL_TXT_BIOSACM_ALIGNMENT
287 hex
288 default 0x40000 # 256KB
289
Wim Vervoorn2ab4f4b2019-10-23 10:22:06 +0200[diff] [blame]290config MAINBOARD_SUPPORTS_SKYLAKE_CPU
291 bool "Board can contain Skylake CPU"
292 default y
293
294if SKYLAKE_SOC_PCH_H
295
296config MAINBOARD_SUPPORTS_KABYLAKE_CPU
297 bool "Board can contain Kaby Lake CPU"
298 default y if SOC_INTEL_KABYLAKE
299
300endif
301
302if !SKYLAKE_SOC_PCH_H
303
304config MAINBOARD_SUPPORTS_KABYLAKE_DUAL
305 bool "Board can contain Kaby Lake DUAL core"
306 default y
307
308config MAINBOARD_SUPPORTS_KABYLAKE_QUAD
309 bool "Board can contain Kaby Lake QUAD core"
310 default y
311
312endif
313
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]314endif