Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 2 | |
| 3 | #ifndef SOUTHBRIDGE_INTEL_BD82X6X_PCH_H |
| 4 | #define SOUTHBRIDGE_INTEL_BD82X6X_PCH_H |
| 5 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 6 | #include <acpi/acpi.h> |
Aaron Durbin | 340898f | 2016-07-13 23:22:28 -0500 | [diff] [blame] | 7 | |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 8 | /* PCH types */ |
| 9 | #define PCH_TYPE_CPT 0x1c /* CougarPoint */ |
| 10 | #define PCH_TYPE_PPT 0x1e /* IvyBridge */ |
| 11 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 12 | /* PCH stepping values for LPC device */ |
| 13 | #define PCH_STEP_A0 0 |
| 14 | #define PCH_STEP_A1 1 |
| 15 | #define PCH_STEP_B0 2 |
| 16 | #define PCH_STEP_B1 3 |
| 17 | #define PCH_STEP_B2 4 |
| 18 | #define PCH_STEP_B3 5 |
| 19 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 20 | #define SMBUS_SLAVE_ADDR 0x24 |
| 21 | /* TODO Make sure these don't get changed by stage2 */ |
| 22 | #define DEFAULT_GPIOBASE 0x0480 |
| 23 | #define DEFAULT_PMBASE 0x0500 |
| 24 | |
Elyes Haouas | 35c3ae3b | 2022-10-27 12:25:12 +0200 | [diff] [blame] | 25 | #include <southbridge/intel/common/rcba.h> /* IWYU pragma: export */ |
Arthur Heymans | 58a8953 | 2018-06-12 22:58:19 +0200 | [diff] [blame] | 26 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 27 | #if CONFIG(SOUTHBRIDGE_INTEL_BD82X6X) |
Aaron Durbin | b0f8151 | 2016-07-25 21:31:41 -0500 | [diff] [blame] | 28 | #define CROS_GPIO_DEVICE_NAME "CougarPoint" |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 29 | #elif CONFIG(SOUTHBRIDGE_INTEL_C216) |
Aaron Durbin | b0f8151 | 2016-07-25 21:31:41 -0500 | [diff] [blame] | 30 | #define CROS_GPIO_DEVICE_NAME "PantherPoint" |
| 31 | #endif |
| 32 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 33 | #ifndef __ACPI__ |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 34 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 35 | int pch_silicon_revision(void); |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 36 | int pch_silicon_type(void); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 37 | void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 38 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 39 | void enable_usb_bar(void); |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 40 | |
Vladimir Serbinenko | 7686a56 | 2014-05-18 11:05:56 +0200 | [diff] [blame] | 41 | void early_thermal_init(void); |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 42 | void southbridge_configure_default_intmap(void); |
Nico Huber | ff4025c | 2018-01-14 12:34:43 +0100 | [diff] [blame] | 43 | void southbridge_rcba_config(void); |
Arthur Heymans | 9c53834 | 2019-11-12 16:42:33 +0100 | [diff] [blame] | 44 | /* Optional mainboard hook to do additional configuration |
| 45 | on the RCBA config space. It is called after the raminit. */ |
| 46 | void mainboard_late_rcba_config(void); |
Arthur Heymans | 2b28a16 | 2019-11-12 17:21:08 +0100 | [diff] [blame] | 47 | /* Optional mainboard hook to do additional LPC configuration |
| 48 | or to override what is set up by default. */ |
| 49 | void mainboard_pch_lpc_setup(void); |
Vladimir Serbinenko | 7686a56 | 2014-05-18 11:05:56 +0200 | [diff] [blame] | 50 | void early_pch_init_native(void); |
Patrick Rudolph | 45d4b17 | 2019-03-24 12:27:31 +0100 | [diff] [blame] | 51 | void early_pch_init(void); |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 52 | void early_pch_init_native_dmi_pre(void); |
| 53 | void early_pch_init_native_dmi_post(void); |
Vladimir Serbinenko | 3dc12c1 | 2014-09-17 02:38:51 +0200 | [diff] [blame] | 54 | |
| 55 | struct southbridge_usb_port |
| 56 | { |
| 57 | int enabled; |
| 58 | int current; |
| 59 | int oc_pin; |
| 60 | }; |
| 61 | |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 62 | void pch_enable(struct device *dev); |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 63 | extern const struct southbridge_usb_port mainboard_usb_ports[14]; |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 64 | |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 65 | void early_usb_init(const struct southbridge_usb_port *portmap); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 66 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 67 | /* PCI Configuration Space (D30:F0): PCI2PCI */ |
| 68 | #define PSTS 0x06 |
| 69 | #define SMLT 0x1b |
| 70 | #define SECSTS 0x1e |
| 71 | #define INTR 0x3c |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 72 | |
| 73 | #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) |
| 74 | #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) |
| 75 | #define PCH_ME_DEV PCI_DEV(0, 0x16, 0) |
Angel Pons | ec99cd9 | 2021-01-28 14:20:36 +0100 | [diff] [blame] | 76 | #define PCH_THERMAL_DEV PCI_DEV(0, 0x1f, 6) |
Nico Huber | b2dae79 | 2015-10-26 12:34:02 +0100 | [diff] [blame] | 77 | #define PCH_IOAPIC_PCI_BUS 250 |
| 78 | #define PCH_IOAPIC_PCI_SLOT 31 |
| 79 | #define PCH_HPET_PCI_BUS 250 |
| 80 | #define PCH_HPET_PCI_SLOT 15 |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 81 | |
Patrick Rudolph | 873178b | 2023-10-02 07:06:45 +0200 | [diff] [blame^] | 82 | /* PCI Configuration Space (D28:F0): PCI2PCI */ |
| 83 | #define PCH_PCIE_DEV_SLOT 28 |
| 84 | #define PCH_PCIE_DEV(_func) PCI_DEV(0, PCH_PCIE_DEV_SLOT, _func) |
| 85 | |
Angel Pons | 2fa7f07 | 2021-01-06 00:48:39 +0100 | [diff] [blame] | 86 | /* PCI Configuration Space (D20:F0): xHCI */ |
| 87 | #define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0) |
| 88 | |
| 89 | #define XHCI_PWR_CNTL_STS 0x74 |
| 90 | |
| 91 | /* xHCI memory base registers */ |
| 92 | #define XHCI_PORTSC_x_USB3(port) (0x4c0 + (port) * 0x10) |
| 93 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 94 | /* PCI Configuration Space (D31:F0): LPC */ |
| 95 | #define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) |
| 96 | #define SERIRQ_CNTL 0x64 |
| 97 | |
| 98 | #define GEN_PMCON_1 0xa0 |
| 99 | #define GEN_PMCON_2 0xa2 |
| 100 | #define GEN_PMCON_3 0xa4 |
Patrick Rudolph | c368620 | 2017-05-03 17:50:00 +0200 | [diff] [blame] | 101 | #define GEN_PMCON_LOCK 0xa6 |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 102 | #define ETR3 0xac |
| 103 | #define ETR3_CWORWRE (1 << 18) |
| 104 | #define ETR3_CF9GR (1 << 20) |
Patrick Rudolph | 7565cf1 | 2017-05-03 18:38:21 +0200 | [diff] [blame] | 105 | #define ETR3_CF9LOCK (1 << 31) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 106 | |
| 107 | /* GEN_PMCON_3 bits */ |
| 108 | #define RTC_BATTERY_DEAD (1 << 2) |
| 109 | #define RTC_POWER_FAILED (1 << 1) |
| 110 | #define SLEEP_AFTER_POWER_FAIL (1 << 0) |
| 111 | |
| 112 | #define PMBASE 0x40 |
| 113 | #define ACPI_CNTL 0x44 |
Paul Menzel | 9c50e6a | 2013-05-03 12:23:39 +0200 | [diff] [blame] | 114 | #define ACPI_EN (1 << 7) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 115 | #define BIOS_CNTL 0xDC |
| 116 | #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ |
| 117 | #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ |
Kyösti Mälkki | b85a87b | 2014-12-29 11:32:27 +0200 | [diff] [blame] | 118 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 119 | #define GPIO_ROUT 0xb8 |
Kyösti Mälkki | b85a87b | 2014-12-29 11:32:27 +0200 | [diff] [blame] | 120 | #define GPI_DISABLE 0x00 |
| 121 | #define GPI_IS_SMI 0x01 |
| 122 | #define GPI_IS_SCI 0x02 |
| 123 | #define GPI_IS_NMI 0x03 |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 124 | |
| 125 | #define PIRQA_ROUT 0x60 |
| 126 | #define PIRQB_ROUT 0x61 |
| 127 | #define PIRQC_ROUT 0x62 |
| 128 | #define PIRQD_ROUT 0x63 |
| 129 | #define PIRQE_ROUT 0x68 |
| 130 | #define PIRQF_ROUT 0x69 |
| 131 | #define PIRQG_ROUT 0x6A |
| 132 | #define PIRQH_ROUT 0x6B |
| 133 | |
Nico Huber | b2dae79 | 2015-10-26 12:34:02 +0100 | [diff] [blame] | 134 | #define LPC_IBDF 0x6C /* I/O APIC bus/dev/fn */ |
| 135 | #define LPC_HnBDF(n) (0x70 + n * 2) /* HPET n bus/dev/fn */ |
| 136 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 137 | #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ |
| 138 | #define LPC_EN 0x82 /* LPC IF Enables Register */ |
| 139 | #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ |
| 140 | #define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ |
| 141 | #define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ |
| 142 | #define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ |
| 143 | #define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ |
| 144 | #define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ |
| 145 | #define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ |
| 146 | #define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ |
| 147 | #define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ |
| 148 | #define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ |
| 149 | #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ |
| 150 | #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ |
| 151 | #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ |
| 152 | #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ |
Peter Lemenkov | 9b7ae2f | 2018-10-09 13:09:07 +0200 | [diff] [blame] | 153 | #define LGMR 0x98 /* LPC Generic Memory Range */ |
| 154 | #define BIOS_DEC_EN1 0xd8 /* BIOS Decode Enable */ |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 155 | |
Angel Pons | 0b3512b | 2020-08-10 13:02:20 +0200 | [diff] [blame] | 156 | /* PCI Configuration Space (D31:F2): SATA */ |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 157 | #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) |
| 158 | #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 159 | #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ |
| 160 | #define IDE_DECODE_ENABLE (1 << 15) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 161 | #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ |
| 162 | |
Stefan Reinauer | 16b022a | 2012-07-17 16:42:51 -0700 | [diff] [blame] | 163 | #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ |
| 164 | #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 165 | #define SATA_SP 0xd0 /* Scratchpad */ |
| 166 | |
Duncan Laurie | cfb64bd | 2012-07-16 16:16:31 -0700 | [diff] [blame] | 167 | /* SATA IOBP Registers */ |
| 168 | #define SATA_IOBP_SP0G3IR 0xea000151 |
| 169 | #define SATA_IOBP_SP1G3IR 0xea000051 |
| 170 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 171 | /* PCI Configuration Space (D31:F3): SMBus */ |
| 172 | #define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3) |
| 173 | #define SMB_BASE 0x20 |
| 174 | #define HOSTC 0x40 |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 175 | |
| 176 | /* HOSTC bits */ |
| 177 | #define I2C_EN (1 << 2) |
| 178 | #define SMB_SMI_EN (1 << 1) |
| 179 | #define HST_EN (1 << 0) |
| 180 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 181 | /* Southbridge IO BARs */ |
| 182 | |
| 183 | #define GPIOBASE 0x48 |
| 184 | |
| 185 | #define PMBASE 0x40 |
| 186 | |
Patrick Rudolph | 4f8b108 | 2019-07-14 11:54:58 +0200 | [diff] [blame] | 187 | #define CIR0 0x0050 /* 32bit */ |
| 188 | #define TCLOCKDN (1u << 31) |
Arthur Heymans | 58a8953 | 2018-06-12 22:58:19 +0200 | [diff] [blame] | 189 | |
Arthur Heymans | 58a8953 | 2018-06-12 22:58:19 +0200 | [diff] [blame] | 190 | #define RPC 0x0400 /* 32bit */ |
| 191 | #define RPFN 0x0404 /* 32bit */ |
| 192 | |
Patrick Rudolph | 4f8b108 | 2019-07-14 11:54:58 +0200 | [diff] [blame] | 193 | #define CIR2 0x900 /* 16bit */ |
| 194 | #define CIR3 0x1100 /* 16bit */ |
| 195 | #define UPDCR 0x1114 /* 32bit */ |
| 196 | |
Arthur Heymans | 58a8953 | 2018-06-12 22:58:19 +0200 | [diff] [blame] | 197 | /* Root Port configuratinon space hide */ |
| 198 | #define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) |
| 199 | /* Get the function number assigned to a Root Port */ |
| 200 | #define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7) |
| 201 | /* Set the function number for a Root Port */ |
| 202 | #define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4)) |
| 203 | /* Root Port function number mask */ |
| 204 | #define RPFN_FNMASK(port) (7 << ((port) * 4)) |
| 205 | |
| 206 | #define TRSR 0x1e00 /* 8bit */ |
| 207 | #define TRCR 0x1e10 /* 64bit */ |
| 208 | #define TWDR 0x1e18 /* 64bit */ |
| 209 | |
| 210 | #define IOTR0 0x1e80 /* 64bit */ |
| 211 | #define IOTR1 0x1e88 /* 64bit */ |
| 212 | #define IOTR2 0x1e90 /* 64bit */ |
| 213 | #define IOTR3 0x1e98 /* 64bit */ |
| 214 | |
Patrick Rudolph | bf74350 | 2019-03-25 17:05:20 +0100 | [diff] [blame] | 215 | #define VCNEGPND 2 |
| 216 | |
Arthur Heymans | 58a8953 | 2018-06-12 22:58:19 +0200 | [diff] [blame] | 217 | #define TCTL 0x3000 /* 8bit */ |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 218 | |
| 219 | #define NOINT 0 |
| 220 | #define INTA 1 |
| 221 | #define INTB 2 |
| 222 | #define INTC 3 |
| 223 | #define INTD 4 |
| 224 | |
| 225 | #define DIR_IDR 12 /* Interrupt D Pin Offset */ |
| 226 | #define DIR_ICR 8 /* Interrupt C Pin Offset */ |
| 227 | #define DIR_IBR 4 /* Interrupt B Pin Offset */ |
| 228 | #define DIR_IAR 0 /* Interrupt A Pin Offset */ |
| 229 | |
| 230 | #define PIRQA 0 |
| 231 | #define PIRQB 1 |
| 232 | #define PIRQC 2 |
| 233 | #define PIRQD 3 |
| 234 | #define PIRQE 4 |
| 235 | #define PIRQF 5 |
| 236 | #define PIRQG 6 |
| 237 | #define PIRQH 7 |
| 238 | |
Patrick Rudolph | 4f8b108 | 2019-07-14 11:54:58 +0200 | [diff] [blame] | 239 | /* DMI control */ |
| 240 | #define V0CTL 0x2014 /* 32bit */ |
| 241 | #define V0STS 0x201a /* 16bit */ |
| 242 | #define V1CTL 0x2020 /* 32bit */ |
| 243 | #define V1STS 0x2026 /* 16bit */ |
| 244 | #define CIR31 0x2030 /* 32bit */ |
| 245 | #define CIR32 0x2040 /* 32bit */ |
| 246 | #define CIR1 0x2088 /* 32bit */ |
| 247 | #define REC 0x20ac /* 32bit */ |
| 248 | #define LCAP 0x21a4 /* 32bit */ |
| 249 | #define LCTL 0x21a8 /* 16bit */ |
| 250 | #define LSTS 0x21aa /* 16bit */ |
| 251 | #define DLCTL2 0x21b0 /* 16bit */ |
| 252 | #define DMIC 0x2234 /* 32bit */ |
| 253 | #define CIR30 0x2238 /* 32bit */ |
| 254 | #define CIR5 0x228c /* 32bit */ |
| 255 | #define DMC 0x2304 /* 32bit */ |
| 256 | #define CIR6 0x2314 /* 32bit */ |
| 257 | #define CIR9 0x2320 /* 32bit */ |
| 258 | #define DMC2 0x2324 /* 32bit - name guessed */ |
| 259 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 260 | /* IO Buffer Programming */ |
| 261 | #define IOBPIRI 0x2330 |
| 262 | #define IOBPD 0x2334 |
| 263 | #define IOBPS 0x2338 |
| 264 | #define IOBPS_RW_BX ((1 << 9)|(1 << 10)) |
| 265 | #define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) |
| 266 | #define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10)) |
| 267 | |
Arthur Heymans | 58a8953 | 2018-06-12 22:58:19 +0200 | [diff] [blame] | 268 | #define D31IP 0x3100 /* 32bit */ |
| 269 | #define D31IP_TTIP 24 /* Thermal Throttle Pin */ |
| 270 | #define D31IP_SIP2 20 /* SATA Pin 2 */ |
| 271 | #define D31IP_SMIP 12 /* SMBUS Pin */ |
| 272 | #define D31IP_SIP 8 /* SATA Pin */ |
| 273 | #define D30IP 0x3104 /* 32bit */ |
| 274 | #define D30IP_PIP 0 /* PCI Bridge Pin */ |
| 275 | #define D29IP 0x3108 /* 32bit */ |
| 276 | #define D29IP_E1P 0 /* EHCI #1 Pin */ |
| 277 | #define D28IP 0x310c /* 32bit */ |
| 278 | #define D28IP_P8IP 28 /* PCI Express Port 8 */ |
| 279 | #define D28IP_P7IP 24 /* PCI Express Port 7 */ |
| 280 | #define D28IP_P6IP 20 /* PCI Express Port 6 */ |
| 281 | #define D28IP_P5IP 16 /* PCI Express Port 5 */ |
| 282 | #define D28IP_P4IP 12 /* PCI Express Port 4 */ |
| 283 | #define D28IP_P3IP 8 /* PCI Express Port 3 */ |
| 284 | #define D28IP_P2IP 4 /* PCI Express Port 2 */ |
| 285 | #define D28IP_P1IP 0 /* PCI Express Port 1 */ |
| 286 | #define D27IP 0x3110 /* 32bit */ |
| 287 | #define D27IP_ZIP 0 /* HD Audio Pin */ |
| 288 | #define D26IP 0x3114 /* 32bit */ |
| 289 | #define D26IP_E2P 0 /* EHCI #2 Pin */ |
| 290 | #define D25IP 0x3118 /* 32bit */ |
| 291 | #define D25IP_LIP 0 /* GbE LAN Pin */ |
| 292 | #define D22IP 0x3124 /* 32bit */ |
| 293 | #define D22IP_KTIP 12 /* KT Pin */ |
| 294 | #define D22IP_IDERIP 8 /* IDE-R Pin */ |
| 295 | #define D22IP_MEI2IP 4 /* MEI #2 Pin */ |
| 296 | #define D22IP_MEI1IP 0 /* MEI #1 Pin */ |
| 297 | #define D20IP 0x3128 /* 32bit */ |
| 298 | #define D20IP_XHCIIP 0 |
| 299 | #define D31IR 0x3140 /* 16bit */ |
| 300 | #define D30IR 0x3142 /* 16bit */ |
| 301 | #define D29IR 0x3144 /* 16bit */ |
| 302 | #define D28IR 0x3146 /* 16bit */ |
| 303 | #define D27IR 0x3148 /* 16bit */ |
| 304 | #define D26IR 0x314c /* 16bit */ |
| 305 | #define D25IR 0x3150 /* 16bit */ |
| 306 | #define D22IR 0x315c /* 16bit */ |
| 307 | #define D20IR 0x3160 /* 16bit */ |
| 308 | #define OIC 0x31fe /* 16bit */ |
Duncan Laurie | 22935e1 | 2012-07-09 09:58:35 -0700 | [diff] [blame] | 309 | #define SOFT_RESET_CTRL 0x38f4 |
| 310 | #define SOFT_RESET_DATA 0x38f8 |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 311 | |
Arthur Heymans | 58a8953 | 2018-06-12 22:58:19 +0200 | [diff] [blame] | 312 | #define DIR_ROUTE(x,a,b,c,d) \ |
| 313 | RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ |
| 314 | ((b) << DIR_IBR) | ((a) << DIR_IAR)) |
| 315 | |
Patrick Rudolph | 4f8b108 | 2019-07-14 11:54:58 +0200 | [diff] [blame] | 316 | #define PRSTS 0x3310 /* 32bit */ |
| 317 | #define CIR7 0x3314 /* 32bit */ |
| 318 | #define PM_CFG 0x3318 /* 32bit */ |
| 319 | #define CIR8 0x3324 /* 32bit */ |
| 320 | #define CIR10 0x3340 /* 32bit */ |
| 321 | #define CIR11 0x3344 /* 32bit */ |
| 322 | #define CIR12 0x3360 /* 32bit */ |
| 323 | #define CIR14 0x3368 /* 32bit */ |
| 324 | #define CIR15 0x3378 /* 32bit */ |
| 325 | #define CIR13 0x337c /* 32bit */ |
| 326 | #define CIR16 0x3388 /* 32bit */ |
| 327 | #define CIR18 0x3390 /* 32bit */ |
| 328 | #define CIR17 0x33a0 /* 32bit */ |
| 329 | #define CIR23 0x33b0 /* 32bit */ |
| 330 | #define CIR19 0x33c0 /* 32bit */ |
| 331 | #define PMSYNC_CFG 0x33c8 /* 32bit */ |
| 332 | #define CIR20 0x33cc /* 32bit */ |
| 333 | #define CIR21 0x33d0 /* 32bit */ |
| 334 | #define CIR22 0x33d4 /* 32bit */ |
| 335 | |
Arthur Heymans | 58a8953 | 2018-06-12 22:58:19 +0200 | [diff] [blame] | 336 | #define RC 0x3400 /* 32bit */ |
| 337 | #define HPTC 0x3404 /* 32bit */ |
| 338 | #define GCS 0x3410 /* 32bit */ |
| 339 | #define BUC 0x3414 /* 32bit */ |
| 340 | #define PCH_DISABLE_GBE (1 << 5) |
| 341 | #define FD 0x3418 /* 32bit */ |
| 342 | #define DISPBDF 0x3424 /* 16bit */ |
| 343 | #define FD2 0x3428 /* 32bit */ |
| 344 | #define CG 0x341c /* 32bit */ |
| 345 | |
| 346 | /* Function Disable 1 RCBA 0x3418 */ |
| 347 | #define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)) |
| 348 | #define PCH_DISABLE_P2P (1 << 1) |
| 349 | #define PCH_DISABLE_SATA1 (1 << 2) |
| 350 | #define PCH_DISABLE_SMBUS (1 << 3) |
| 351 | #define PCH_DISABLE_HD_AUDIO (1 << 4) |
| 352 | #define PCH_DISABLE_EHCI2 (1 << 13) |
| 353 | #define PCH_DISABLE_LPC (1 << 14) |
| 354 | #define PCH_DISABLE_EHCI1 (1 << 15) |
| 355 | #define PCH_DISABLE_PCIE(x) (1 << (16 + x)) |
| 356 | #define PCH_DISABLE_THERMAL (1 << 24) |
| 357 | #define PCH_DISABLE_SATA2 (1 << 25) |
| 358 | #define PCH_DISABLE_XHCI (1 << 27) |
| 359 | |
| 360 | /* Function Disable 2 RCBA 0x3428 */ |
| 361 | #define PCH_DISABLE_KT (1 << 4) |
| 362 | #define PCH_DISABLE_IDER (1 << 3) |
| 363 | #define PCH_DISABLE_MEI2 (1 << 2) |
| 364 | #define PCH_DISABLE_MEI1 (1 << 1) |
| 365 | #define PCH_ENABLE_DBDF (1 << 0) |
| 366 | |
Patrick Rudolph | 4f8b108 | 2019-07-14 11:54:58 +0200 | [diff] [blame] | 367 | /* USB Initialization Registers[13:0] */ |
| 368 | #define USBIR0 0x3500 /* 32bit */ |
| 369 | #define USBIR1 0x3504 /* 32bit */ |
| 370 | #define USBIR2 0x3508 /* 32bit */ |
| 371 | #define USBIR3 0x350c /* 32bit */ |
| 372 | #define USBIR4 0x3510 /* 32bit */ |
| 373 | #define USBIR5 0x3514 /* 32bit */ |
| 374 | #define USBIR6 0x3518 /* 32bit */ |
| 375 | #define USBIR7 0x351c /* 32bit */ |
| 376 | #define USBIR8 0x3520 /* 32bit */ |
| 377 | #define USBIR9 0x3524 /* 32bit */ |
| 378 | #define USBIR10 0x3528 /* 32bit */ |
| 379 | #define USBIR11 0x352c /* 32bit */ |
| 380 | #define USBIR12 0x3530 /* 32bit */ |
| 381 | #define USBIR13 0x3534 /* 32bit */ |
| 382 | |
| 383 | /* Miscellaneous Control Register */ |
| 384 | #define MISCCTL 0x3590 /* 32bit */ |
Nicolas Reinecke | 6d1158f | 2015-01-29 15:48:27 +0100 | [diff] [blame] | 385 | /* USB Port Disable Override */ |
| 386 | #define USBPDO 0x359c /* 32bit */ |
| 387 | /* USB Overcurrent MAP Register */ |
| 388 | #define USBOCM1 0x35a0 /* 32bit */ |
| 389 | #define USBOCM2 0x35a4 /* 32bit */ |
Patrick Rudolph | 4f8b108 | 2019-07-14 11:54:58 +0200 | [diff] [blame] | 390 | /* Rate Matching Hub Wake Control Register */ |
| 391 | #define RMHWKCTL 0x35b0 /* 32bit */ |
| 392 | |
| 393 | #define CIR24 0x3a28 /* 32bit */ |
| 394 | #define CIR25 0x3a2c /* 32bit */ |
| 395 | #define CIR26 0x3a6c /* 32bit */ |
| 396 | #define CIR27 0x3a80 /* 32bit */ |
| 397 | #define CIR28 0x3a84 /* 32bit */ |
| 398 | #define CIR29 0x3a88 /* 32bit */ |
Nicolas Reinecke | 6d1158f | 2015-01-29 15:48:27 +0100 | [diff] [blame] | 399 | |
Nicolas Reinecke | 0b29a7b | 2015-03-29 17:51:11 +0200 | [diff] [blame] | 400 | /* XHCI USB 3.0 */ |
Nicolas Reinecke | 59aef5c | 2015-04-16 23:25:00 +0200 | [diff] [blame] | 401 | #define XOCM 0xc0 /* 32bit */ |
Nicolas Reinecke | 0b29a7b | 2015-03-29 17:51:11 +0200 | [diff] [blame] | 402 | #define XUSB2PRM 0xd4 /* 32bit */ |
| 403 | #define USB3PRM 0xdc /* 32bit */ |
| 404 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 405 | /* ICH7 PMBASE */ |
| 406 | #define PM1_STS 0x00 |
| 407 | #define WAK_STS (1 << 15) |
| 408 | #define PCIEXPWAK_STS (1 << 14) |
| 409 | #define PRBTNOR_STS (1 << 11) |
| 410 | #define RTC_STS (1 << 10) |
| 411 | #define PWRBTN_STS (1 << 8) |
| 412 | #define GBL_STS (1 << 5) |
| 413 | #define BM_STS (1 << 4) |
| 414 | #define TMROF_STS (1 << 0) |
| 415 | #define PM1_EN 0x02 |
| 416 | #define PCIEXPWAK_DIS (1 << 14) |
| 417 | #define RTC_EN (1 << 10) |
| 418 | #define PWRBTN_EN (1 << 8) |
| 419 | #define GBL_EN (1 << 5) |
| 420 | #define TMROF_EN (1 << 0) |
| 421 | #define PM1_CNT 0x04 |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 422 | #define GBL_RLS (1 << 2) |
| 423 | #define BM_RLD (1 << 1) |
| 424 | #define SCI_EN (1 << 0) |
| 425 | #define PM1_TMR 0x08 |
| 426 | #define PROC_CNT 0x10 |
| 427 | #define LV2 0x14 |
| 428 | #define LV3 0x15 |
| 429 | #define LV4 0x16 |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 430 | #define GPE0_STS 0x20 |
| 431 | #define PME_B0_STS (1 << 13) |
| 432 | #define PME_STS (1 << 11) |
| 433 | #define BATLOW_STS (1 << 10) |
| 434 | #define PCI_EXP_STS (1 << 9) |
| 435 | #define RI_STS (1 << 8) |
| 436 | #define SMB_WAK_STS (1 << 7) |
| 437 | #define TCOSCI_STS (1 << 6) |
| 438 | #define SWGPE_STS (1 << 2) |
| 439 | #define HOT_PLUG_STS (1 << 1) |
| 440 | #define GPE0_EN 0x28 |
| 441 | #define PME_B0_EN (1 << 13) |
| 442 | #define PME_EN (1 << 11) |
Stefan Reinauer | 9d81c19 | 2012-09-19 10:49:12 -0700 | [diff] [blame] | 443 | #define TCOSCI_EN (1 << 6) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 444 | #define SMI_EN 0x30 |
| 445 | #define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic |
| 446 | #define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic |
| 447 | #define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS |
| 448 | #define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) |
| 449 | #define MCSMI_EN (1 << 11) // Trap microcontroller range access |
| 450 | #define BIOS_RLS (1 << 7) // asserts SCI on bit set |
| 451 | #define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set |
| 452 | #define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# |
| 453 | #define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# |
| 454 | #define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic |
| 455 | #define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit |
| 456 | #define EOS (1 << 1) // End of SMI (deassert SMI#) |
| 457 | #define GBL_SMI_EN (1 << 0) // SMI# generation at all? |
| 458 | #define SMI_STS 0x34 |
| 459 | #define ALT_GP_SMI_EN 0x38 |
| 460 | #define ALT_GP_SMI_STS 0x3a |
Kyösti Mälkki | ece06dc | 2023-05-05 09:27:42 +0300 | [diff] [blame] | 461 | |
| 462 | /* PM I/O Space */ |
| 463 | #define UPRWC 0x3c |
| 464 | #define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ |
| 465 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 466 | #define GPE_CNTL 0x42 |
| 467 | #define DEVACT_STS 0x44 |
Kyösti Mälkki | 806b2cd | 2022-11-14 17:46:30 +0200 | [diff] [blame] | 468 | #define PM2_CNT 0x50 // mobile only |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 469 | #define C3_RES 0x54 |
Kyösti Mälkki | 806b2cd | 2022-11-14 17:46:30 +0200 | [diff] [blame] | 470 | |
Kyösti Mälkki | e8a3af1 | 2022-11-19 18:39:22 +0200 | [diff] [blame] | 471 | #if CONFIG(TCO_SPACE_NOT_YET_SPLIT) |
Duncan Laurie | 800e950 | 2012-06-23 17:06:47 -0700 | [diff] [blame] | 472 | #define TCO1_STS 0x64 |
Kyösti Mälkki | 28c6df7 | 2022-11-25 12:12:34 +0200 | [diff] [blame] | 473 | #define TCO_TIMEOUT (1 << 3) |
Stefan Reinauer | 9d81c19 | 2012-09-19 10:49:12 -0700 | [diff] [blame] | 474 | #define DMISCI_STS (1 << 9) |
Duncan Laurie | 800e950 | 2012-06-23 17:06:47 -0700 | [diff] [blame] | 475 | #define TCO2_STS 0x66 |
Kyösti Mälkki | 307320c | 2022-11-21 17:27:07 +0200 | [diff] [blame] | 476 | #define TCO2_STS_SECOND_TO (1 << 1) |
Dennis Wassenberg | 0c04720 | 2015-09-10 12:03:45 +0200 | [diff] [blame] | 477 | #define TCO1_CNT 0x68 |
Patrick Rudolph | 48b2425 | 2018-07-27 18:58:06 +0200 | [diff] [blame] | 478 | #define TCO_TMR_HLT (1 << 11) |
Dennis Wassenberg | 0c04720 | 2015-09-10 12:03:45 +0200 | [diff] [blame] | 479 | #define TCO_LOCK (1 << 12) |
| 480 | #define TCO2_CNT 0x6a |
Kyösti Mälkki | e8a3af1 | 2022-11-19 18:39:22 +0200 | [diff] [blame] | 481 | #endif |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 482 | |
Duncan Laurie | d4bc067 | 2012-10-11 13:04:14 -0700 | [diff] [blame] | 483 | #define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ |
| 484 | #define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ |
| 485 | #define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ |
| 486 | #define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ |
| 487 | #define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ |
| 488 | #define SPIBAR_HSFC 0x3806 /* SPI hardware sequence control */ |
| 489 | #define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) |
| 490 | #define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ |
| 491 | #define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ |
| 492 | #define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ |
| 493 | #define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ |
| 494 | #define SPIBAR_FADDR 0x3808 /* SPI flash address */ |
| 495 | #define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */ |
| 496 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 497 | #endif /* __ACPI__ */ |
| 498 | #endif /* SOUTHBRIDGE_INTEL_BD82X6X_PCH_H */ |