sb/intel/bd82x6x: Follow PCH BIOS spec
PCH BIOS spec says that BIOS must clear BIT26 in register 0x338
in PEI, as done on lynxpoint.
Copy and adapt the lynxpoint code to do the same on bd82x6x.
Add special case for UM77 chipset, which only has 4 PCIe ports.
Test: System still boots and all PCIe ports are fully working.
Change-Id: I865818c0c22194fffcb2bbdf8c43737b0dce2307
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 8face06..6d164ea 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -74,12 +74,15 @@
#define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0)
#define PCH_ME_DEV PCI_DEV(0, 0x16, 0)
#define PCH_THERMAL_DEV PCI_DEV(0, 0x1f, 6)
-#define PCH_PCIE_DEV_SLOT 28
#define PCH_IOAPIC_PCI_BUS 250
#define PCH_IOAPIC_PCI_SLOT 31
#define PCH_HPET_PCI_BUS 250
#define PCH_HPET_PCI_SLOT 15
+/* PCI Configuration Space (D28:F0): PCI2PCI */
+#define PCH_PCIE_DEV_SLOT 28
+#define PCH_PCIE_DEV(_func) PCI_DEV(0, PCH_PCIE_DEV_SLOT, _func)
+
/* PCI Configuration Space (D20:F0): xHCI */
#define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0)