| commit | 59aef5c79e7ae85854a88db4803334617d7b83fd | [log] [tgz] |
|---|---|---|
| author | Nicolas Reinecke <nr@das-labor.org> | Thu Apr 16 23:25:00 2015 +0200 |
| committer | Edward O'Callaghan <edward.ocallaghan@koparo.com> | Mon Apr 20 23:50:38 2015 +0200 |
| tree | b0a00b163b009e0772b03003bf287ab62e3ffbee | |
| parent | f21b657f27965beacd2a3134aafbf66d4db60930 [diff] [blame] |
southbrige/intel/bd82x6x: add XHCI overcurrent map config Change-Id: I9a40e5a1028c7674e6dd54742e6646ba48ce7696 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/9449 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 7b52ebc..4ec2903 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -449,6 +449,7 @@ #define USBOCM2 0x35a4 /* 32bit */ /* XHCI USB 3.0 */ +#define XOCM 0xc0 /* 32bit */ #define XUSB2PRM 0xd4 /* 32bit */ #define USB3PRM 0xdc /* 32bit */