| commit | 28c6df73239b6c04c25fba43b072fbb92a348feb | [log] [tgz] |
|---|---|---|
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | Fri Nov 25 12:12:34 2022 +0200 |
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | Mon Nov 28 10:10:26 2022 +0000 |
| tree | 6a89f52cd9508a35f66fe6baa1bff48b269f7d4e | |
| parent | 307320c23f2c1907ff6cf6fa87608d1155aba05f [diff] [blame] |
sb/intel/common: Rename TCO timeout Rename TCO1_TIMEOUT to TCO_TIMEOUT to match rest of the tree. Change-Id: Ib136e9b2d0006eb4ceceb298b557644760d1185c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 3aef48a..8155479 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -466,7 +466,7 @@ #if CONFIG(TCO_SPACE_NOT_YET_SPLIT) #define TCO1_STS 0x64 -#define TCO1_TIMEOUT (1 << 3) +#define TCO_TIMEOUT (1 << 3) #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 #define TCO2_STS_SECOND_TO (1 << 1)