sb/intel/bd82x6x/finalize: Lock ETR3 CF9GR
Lock CF9GR as documented in "100-series-chipset-datasheet-vol-2.pdf"
Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index da1f901..f8131da 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -144,6 +144,7 @@
#define ETR3 0xac
#define ETR3_CWORWRE (1 << 18)
#define ETR3_CF9GR (1 << 20)
+#define ETR3_CF9LOCK (1 << 31)
/* GEN_PMCON_3 bits */
#define RTC_BATTERY_DEAD (1 << 2)