Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2011 Google Inc. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 15 | |
| 16 | config SOUTHBRIDGE_INTEL_BD82X6X |
| 17 | bool |
| 18 | |
| 19 | config SOUTHBRIDGE_INTEL_C216 |
| 20 | bool |
| 21 | |
| 22 | if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 |
| 23 | |
| 24 | config SOUTH_BRIDGE_OPTIONS # dummy |
| 25 | def_bool y |
Aaron Durbin | 340898f | 2016-07-13 23:22:28 -0500 | [diff] [blame] | 26 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 27 | select SOUTHBRIDGE_INTEL_COMMON_FINALIZE |
Tobias Diedrich | 7f5efd9 | 2017-12-14 00:29:01 +0100 | [diff] [blame] | 28 | select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 29 | select SOUTHBRIDGE_INTEL_COMMON_SMBUS |
Arthur Heymans | bddef0d | 2017-09-25 12:21:07 +0200 | [diff] [blame] | 30 | select SOUTHBRIDGE_INTEL_COMMON_SPI |
Patrick Rudolph | e2f0a5f | 2019-03-24 14:47:47 +0100 | [diff] [blame] | 31 | select SOUTHBRIDGE_INTEL_COMMON_PMCLIB |
Arthur Heymans | b8bda11 | 2019-06-04 13:57:47 +0200 | [diff] [blame] | 32 | select SOUTHBRIDGE_INTEL_COMMON_PMBASE |
Arthur Heymans | 074730c | 2019-06-04 14:05:53 +0200 | [diff] [blame] | 33 | select SOUTHBRIDGE_INTEL_COMMON_RTC |
Arthur Heymans | 23a6c79 | 2019-10-13 22:36:04 +0200 | [diff] [blame] | 34 | select SOUTHBRIDGE_INTEL_COMMON_RESET |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 35 | select IOAPIC |
Kyösti Mälkki | 545b30d | 2013-06-13 13:51:14 +0300 | [diff] [blame] | 36 | select HAVE_USBDEBUG_OPTIONS |
Stefan Reinauer | 431a816 | 2012-11-13 13:01:31 -0800 | [diff] [blame] | 37 | select HAVE_SMI_HANDLER |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 38 | select USE_WATCHDOG_ON_BOOT |
| 39 | select PCIEXP_ASPM |
| 40 | select PCIEXP_COMMON_CLOCK |
Vladimir Serbinenko | 5b044ae | 2014-10-25 15:20:55 +0200 | [diff] [blame] | 41 | select COMMON_FADT |
Alexander Couzens | 7bf47ee | 2015-04-16 02:00:21 +0200 | [diff] [blame] | 42 | select ACPI_SATA_GENERATOR |
Stefan Tauner | ef8b957 | 2018-09-06 00:34:28 +0200 | [diff] [blame] | 43 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Patrick Rudolph | e8e66f4 | 2016-02-06 17:42:42 +0100 | [diff] [blame] | 44 | select SOUTHBRIDGE_INTEL_COMMON_GPIO |
Aaron Durbin | 16246ea | 2016-08-05 21:23:37 -0500 | [diff] [blame] | 45 | select RTC |
Bill XIE | d533b16 | 2017-08-22 16:26:22 +0800 | [diff] [blame] | 46 | select HAVE_INTEL_CHIPSET_LOCKDOWN |
Arthur Heymans | a050817 | 2018-01-25 11:30:22 +0100 | [diff] [blame] | 47 | select SOUTHBRIDGE_INTEL_COMMON_SMM |
Tristan Corrick | 167a512 | 2018-10-31 02:28:32 +1300 | [diff] [blame] | 48 | select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT |
Elyes HAOUAS | 551a759 | 2019-05-01 16:56:36 +0200 | [diff] [blame] | 49 | select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG |
Arthur Heymans | 3457df1 | 2019-11-16 10:04:41 +0100 | [diff] [blame^] | 50 | select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 51 | |
| 52 | config EHCI_BAR |
| 53 | hex |
| 54 | default 0xfef00000 |
| 55 | |
Vladimir Serbinenko | 6a7aeb3 | 2014-01-05 11:37:32 +0100 | [diff] [blame] | 56 | config DRAM_RESET_GATE_GPIO |
| 57 | int |
| 58 | default 60 |
| 59 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 60 | config BOOTBLOCK_SOUTHBRIDGE_INIT |
| 61 | string |
| 62 | default "southbridge/intel/bd82x6x/bootblock.c" |
| 63 | |
| 64 | config SERIRQ_CONTINUOUS_MODE |
| 65 | bool |
| 66 | default n |
| 67 | help |
| 68 | If you set this option to y, the serial IRQ machine will be |
| 69 | operated in continuous mode. |
| 70 | |
Patrick Georgi | 9aeb694 | 2012-10-05 21:54:38 +0200 | [diff] [blame] | 71 | config HPET_MIN_TICKS |
| 72 | hex |
| 73 | default 0x80 |
| 74 | |
Vladimir Serbinenko | d3b194e | 2015-05-12 12:39:53 +0200 | [diff] [blame] | 75 | endif |