blob: 6bb488c8b36f8c308717fdbf9cb6d1044f0bab88 [file] [log] [blame]
Stefan Reinauer8e073822012-04-04 00:07:22 +02001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2011 Google Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
Stefan Reinauer8e073822012-04-04 00:07:22 +020015
16config SOUTHBRIDGE_INTEL_BD82X6X
17 bool
18
19config SOUTHBRIDGE_INTEL_C216
20 bool
21
22if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216
23
24config SOUTH_BRIDGE_OPTIONS # dummy
25 def_bool y
Kyösti Mälkki71216c92013-07-28 23:39:37 +030026 select SOUTHBRIDGE_INTEL_COMMON
Stefan Reinauer8e073822012-04-04 00:07:22 +020027 select IOAPIC
28 select HAVE_HARD_RESET
Kyösti Mälkki545b30d2013-06-13 13:51:14 +030029 select HAVE_USBDEBUG_OPTIONS
Stefan Reinauer431a8162012-11-13 13:01:31 -080030 select HAVE_SMI_HANDLER
Stefan Reinauer8e073822012-04-04 00:07:22 +020031 select USE_WATCHDOG_ON_BOOT
32 select PCIEXP_ASPM
33 select PCIEXP_COMMON_CLOCK
Stefan Reinauer1c56d9b2012-05-10 11:27:32 -070034 select SPI_FLASH
Vladimir Serbinenko5b044ae2014-10-25 15:20:55 +020035 select COMMON_FADT
Alexander Couzens7bf47ee2015-04-16 02:00:21 +020036 select ACPI_SATA_GENERATOR
Martin Roth3fda3c22015-07-09 21:02:26 -060037 select HAVE_INTEL_FIRMWARE
Patrick Rudolphe8e66f42016-02-06 17:42:42 +010038 select SOUTHBRIDGE_INTEL_COMMON_GPIO
Stefan Reinauer8e073822012-04-04 00:07:22 +020039
40config EHCI_BAR
41 hex
42 default 0xfef00000
43
Vladimir Serbinenko6a7aeb32014-01-05 11:37:32 +010044config DRAM_RESET_GATE_GPIO
45 int
46 default 60
47
Stefan Reinauer8e073822012-04-04 00:07:22 +020048config BOOTBLOCK_SOUTHBRIDGE_INIT
49 string
50 default "southbridge/intel/bd82x6x/bootblock.c"
51
52config SERIRQ_CONTINUOUS_MODE
53 bool
54 default n
55 help
56 If you set this option to y, the serial IRQ machine will be
57 operated in continuous mode.
58
Patrick Georgi9aeb6942012-10-05 21:54:38 +020059config HPET_MIN_TICKS
60 hex
61 default 0x80
62
Nico Hubera15cd662013-06-19 16:16:05 +020063config HAVE_IFD_BIN
Martin Roth3fda3c22015-07-09 21:02:26 -060064 def_bool y
Nico Hubera15cd662013-06-19 16:16:05 +020065
66config BUILD_WITH_FAKE_IFD
Martin Roth3fda3c22015-07-09 21:02:26 -060067 def_bool !HAVE_IFD_BIN
Stefan Reinauer7004b7c2012-10-31 17:30:13 -070068
Vladimir Serbinenkod3b194e2015-05-12 12:39:53 +020069endif
70
71if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 || SOUTHBRIDGE_INTEL_IBEXPEAK
72
73choice
74 prompt "Flash ROM locking on S3 resume"
75 default LOCK_SPI_ON_RESUME_NONE
76
77config LOCK_SPI_ON_RESUME_NONE
78 bool "Don't lock ROM sections on S3 resume"
79
80config LOCK_SPI_ON_RESUME_RO
Nico Huberd1fb5642013-07-01 16:02:36 +020081 bool "Lock all flash ROM sections on S3 resume"
Nico Huberd1fb5642013-07-01 16:02:36 +020082 help
83 If the flash ROM shall be protected against write accesses from the
84 operating system (OS), the locking procedure has to be repeated after
85 each resume from S3. Select this if you never want to update the flash
86 ROM from within your OS. Notice: Even with this option, the write lock
87 has still to be enabled on the normal boot path (e.g. by the payload).
88
Vladimir Serbinenkod3b194e2015-05-12 12:39:53 +020089config LOCK_SPI_ON_RESUME_NO_ACCESS
90 bool "Lock and disable reads all flash ROM sections on S3 resume"
91 help
92 If the flash ROM shall be protected against all accesses from the
93 operating system (OS), the locking procedure has to be repeated after
94 each resume from S3. Select this if you never want to update the flash
95 ROM from within your OS. Notice: Even with this option, the lock
96 has still to be enabled on the normal boot path (e.g. by the payload).
97
98endchoice
99
Stefan Reinauer8e073822012-04-04 00:07:22 +0200100endif