src/southbridge/intel/bd82x6x/Kconfig

##
## This file is part of the coreboot project.
##
## Copyright (C) 2011 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##

config SOUTHBRIDGE_INTEL_BD82X6X
	bool

config SOUTHBRIDGE_INTEL_C216
	bool

if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216

config SOUTH_BRIDGE_OPTIONS # dummy
	def_bool y
	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
	select SOUTHBRIDGE_INTEL_COMMON
	select SOUTHBRIDGE_INTEL_COMMON_FINALIZE
	select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
	select SOUTHBRIDGE_INTEL_COMMON_SPI
	select SOUTHBRIDGE_INTEL_COMMON_PMCLIB
	select IOAPIC
	select HAVE_USBDEBUG_OPTIONS
	select HAVE_SMI_HANDLER
	select USE_WATCHDOG_ON_BOOT
	select PCIEXP_ASPM
	select PCIEXP_COMMON_CLOCK
	select COMMON_FADT
	select ACPI_SATA_GENERATOR
	select INTEL_DESCRIPTOR_MODE_CAPABLE
	select SOUTHBRIDGE_INTEL_COMMON_GPIO
	select RTC
	select HAVE_INTEL_CHIPSET_LOCKDOWN
	select SOUTHBRIDGE_INTEL_COMMON_SMM
	select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
	select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG

config EHCI_BAR
	hex
	default 0xfef00000

config DRAM_RESET_GATE_GPIO
	int
	default 60

config BOOTBLOCK_SOUTHBRIDGE_INIT
	string
	default "southbridge/intel/bd82x6x/bootblock.c"

config SERIRQ_CONTINUOUS_MODE
	bool
	default n
	help
	  If you set this option to y, the serial IRQ machine will be
	  operated in continuous mode.

config HPET_MIN_TICKS
	hex
	default 0x80

endif