Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2011 Google Inc. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 15 | |
| 16 | config SOUTHBRIDGE_INTEL_BD82X6X |
| 17 | bool |
| 18 | |
| 19 | config SOUTHBRIDGE_INTEL_C216 |
| 20 | bool |
| 21 | |
| 22 | if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 |
| 23 | |
| 24 | config SOUTH_BRIDGE_OPTIONS # dummy |
| 25 | def_bool y |
Aaron Durbin | 340898f | 2016-07-13 23:22:28 -0500 | [diff] [blame] | 26 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Kyösti Mälkki | 71216c9 | 2013-07-28 23:39:37 +0300 | [diff] [blame] | 27 | select SOUTHBRIDGE_INTEL_COMMON |
Tobias Diedrich | 7f5efd9 | 2017-12-14 00:29:01 +0100 | [diff] [blame^] | 28 | select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 29 | select SOUTHBRIDGE_INTEL_COMMON_SMBUS |
Arthur Heymans | bddef0d | 2017-09-25 12:21:07 +0200 | [diff] [blame] | 30 | select SOUTHBRIDGE_INTEL_COMMON_SPI |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 31 | select IOAPIC |
| 32 | select HAVE_HARD_RESET |
Kyösti Mälkki | 545b30d | 2013-06-13 13:51:14 +0300 | [diff] [blame] | 33 | select HAVE_USBDEBUG_OPTIONS |
Stefan Reinauer | 431a816 | 2012-11-13 13:01:31 -0800 | [diff] [blame] | 34 | select HAVE_SMI_HANDLER |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 35 | select USE_WATCHDOG_ON_BOOT |
| 36 | select PCIEXP_ASPM |
| 37 | select PCIEXP_COMMON_CLOCK |
Vladimir Serbinenko | 5b044ae | 2014-10-25 15:20:55 +0200 | [diff] [blame] | 38 | select COMMON_FADT |
Alexander Couzens | 7bf47ee | 2015-04-16 02:00:21 +0200 | [diff] [blame] | 39 | select ACPI_SATA_GENERATOR |
Martin Roth | 3fda3c2 | 2015-07-09 21:02:26 -0600 | [diff] [blame] | 40 | select HAVE_INTEL_FIRMWARE |
Patrick Rudolph | e8e66f4 | 2016-02-06 17:42:42 +0100 | [diff] [blame] | 41 | select SOUTHBRIDGE_INTEL_COMMON_GPIO |
Aaron Durbin | 16246ea | 2016-08-05 21:23:37 -0500 | [diff] [blame] | 42 | select RTC |
Bill XIE | d533b16 | 2017-08-22 16:26:22 +0800 | [diff] [blame] | 43 | select HAVE_INTEL_CHIPSET_LOCKDOWN |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 44 | |
| 45 | config EHCI_BAR |
| 46 | hex |
| 47 | default 0xfef00000 |
| 48 | |
Vladimir Serbinenko | 6a7aeb3 | 2014-01-05 11:37:32 +0100 | [diff] [blame] | 49 | config DRAM_RESET_GATE_GPIO |
| 50 | int |
| 51 | default 60 |
| 52 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 53 | config BOOTBLOCK_SOUTHBRIDGE_INIT |
| 54 | string |
| 55 | default "southbridge/intel/bd82x6x/bootblock.c" |
| 56 | |
| 57 | config SERIRQ_CONTINUOUS_MODE |
| 58 | bool |
| 59 | default n |
| 60 | help |
| 61 | If you set this option to y, the serial IRQ machine will be |
| 62 | operated in continuous mode. |
| 63 | |
Patrick Georgi | 9aeb694 | 2012-10-05 21:54:38 +0200 | [diff] [blame] | 64 | config HPET_MIN_TICKS |
| 65 | hex |
| 66 | default 0x80 |
| 67 | |
Nico Huber | a15cd66 | 2013-06-19 16:16:05 +0200 | [diff] [blame] | 68 | config HAVE_IFD_BIN |
Martin Roth | 3fda3c2 | 2015-07-09 21:02:26 -0600 | [diff] [blame] | 69 | def_bool y |
Nico Huber | a15cd66 | 2013-06-19 16:16:05 +0200 | [diff] [blame] | 70 | |
| 71 | config BUILD_WITH_FAKE_IFD |
Martin Roth | 3fda3c2 | 2015-07-09 21:02:26 -0600 | [diff] [blame] | 72 | def_bool !HAVE_IFD_BIN |
Stefan Reinauer | 7004b7c | 2012-10-31 17:30:13 -0700 | [diff] [blame] | 73 | |
Vladimir Serbinenko | d3b194e | 2015-05-12 12:39:53 +0200 | [diff] [blame] | 74 | endif |
| 75 | |
| 76 | if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 || SOUTHBRIDGE_INTEL_IBEXPEAK |
| 77 | |
| 78 | choice |
Nico Huber | 2ac149d | 2017-09-01 23:28:14 +0200 | [diff] [blame] | 79 | prompt "Flash locking during chipset lockdown" |
| 80 | default LOCK_SPI_FLASH_NONE |
Vladimir Serbinenko | d3b194e | 2015-05-12 12:39:53 +0200 | [diff] [blame] | 81 | |
Nico Huber | 2ac149d | 2017-09-01 23:28:14 +0200 | [diff] [blame] | 82 | config LOCK_SPI_FLASH_NONE |
| 83 | bool "Don't lock flash sections" |
Vladimir Serbinenko | d3b194e | 2015-05-12 12:39:53 +0200 | [diff] [blame] | 84 | |
Nico Huber | 2ac149d | 2017-09-01 23:28:14 +0200 | [diff] [blame] | 85 | config LOCK_SPI_FLASH_RO |
| 86 | bool "Write-protect all flash sections" |
Nico Huber | d1fb564 | 2013-07-01 16:02:36 +0200 | [diff] [blame] | 87 | help |
Nico Huber | 2ac149d | 2017-09-01 23:28:14 +0200 | [diff] [blame] | 88 | Select this if you want to write-protect the whole firmware flash |
| 89 | chip. The locking will take place during the chipset lockdown, which |
| 90 | is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set) |
| 91 | or has to be triggered later (e.g. by the payload or the OS). |
Nico Huber | d1fb564 | 2013-07-01 16:02:36 +0200 | [diff] [blame] | 92 | |
Nico Huber | 2ac149d | 2017-09-01 23:28:14 +0200 | [diff] [blame] | 93 | NOTE: If you trigger the chipset lockdown unconditionally, |
| 94 | you won't be able to write to the flash chip using the |
| 95 | internal programmer any more. |
| 96 | |
| 97 | config LOCK_SPI_FLASH_NO_ACCESS |
| 98 | bool "Write-protect all flash sections and read-protect non-BIOS sections" |
Vladimir Serbinenko | d3b194e | 2015-05-12 12:39:53 +0200 | [diff] [blame] | 99 | help |
Nico Huber | 2ac149d | 2017-09-01 23:28:14 +0200 | [diff] [blame] | 100 | Select this if you want to protect the firmware flash against all |
| 101 | further accesses (with the exception of the memory mapped BIOS re- |
| 102 | gion which is always readable). The locking will take place during |
| 103 | the chipset lockdown, which is either triggered by coreboot (when |
| 104 | INTEL_CHIPSET_LOCKDOWN is set) or has to be triggered later (e.g. |
| 105 | by the payload or the OS). |
| 106 | |
| 107 | NOTE: If you trigger the chipset lockdown unconditionally, |
| 108 | you won't be able to write to the flash chip using the |
| 109 | internal programmer any more. |
Vladimir Serbinenko | d3b194e | 2015-05-12 12:39:53 +0200 | [diff] [blame] | 110 | |
| 111 | endchoice |
| 112 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 113 | endif |