src/southbridge/intel/bd82x6x/Kconfig

##
## This file is part of the coreboot project.
##
## Copyright (C) 2011 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##

config SOUTHBRIDGE_INTEL_BD82X6X
	bool

config SOUTHBRIDGE_INTEL_C216
	bool

if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216

config SOUTH_BRIDGE_OPTIONS # dummy
	def_bool y
	select SOUTHBRIDGE_INTEL_COMMON
	select IOAPIC
	select HAVE_HARD_RESET
	select HAVE_USBDEBUG_OPTIONS
	select HAVE_SMI_HANDLER
	select USE_WATCHDOG_ON_BOOT
	select PCIEXP_ASPM
	select PCIEXP_COMMON_CLOCK
	select SPI_FLASH
	select PER_DEVICE_ACPI_TABLES
	select COMMON_FADT

config EHCI_BAR
	hex
	default 0xfef00000

config DRAM_RESET_GATE_GPIO
	int
	default 60

config BOOTBLOCK_SOUTHBRIDGE_INIT
	string
	default "southbridge/intel/bd82x6x/bootblock.c"

config SERIRQ_CONTINUOUS_MODE
	bool
	default n
	help
	  If you set this option to y, the serial IRQ machine will be
	  operated in continuous mode.

config HPET_MIN_TICKS
	hex
	default 0x80

config HAVE_IFD_BIN
	bool
	default y

config BUILD_WITH_FAKE_IFD
	bool "Build with a fake IFD"
	default y if !HAVE_IFD_BIN
	help
	  If you don't have an Intel Firmware Descriptor (ifd.bin) for your
	  board, you can select this option and coreboot will build without it.
	  Though, the resulting coreboot.rom will not contain all parts required
	  to get coreboot running on your board. You can however write only the
	  BIOS section to your board's flash ROM and keep the other sections
	  untouched. Unfortunately the current version of flashrom doesn't
	  support this yet. But there is a patch pending [1].

	  WARNING: Never write a complete coreboot.rom to your flash ROM if it
	           was built with a fake IFD. It just won't work.

	  [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html

config IFD_BIOS_SECTION
	depends on BUILD_WITH_FAKE_IFD
	string
	default ""

config IFD_ME_SECTION
	depends on BUILD_WITH_FAKE_IFD
	string
	default ""

config IFD_GBE_SECTION
	depends on BUILD_WITH_FAKE_IFD
	string
	default ""

config IFD_PLATFORM_SECTION
	depends on BUILD_WITH_FAKE_IFD
	string
	default ""

config IFD_BIN_PATH
	string "Path to intel firmware descriptor"
	depends on !BUILD_WITH_FAKE_IFD
	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"

config HAVE_GBE_BIN
	bool "Add gigabit ethernet firmware"
	default n
	help
	  The integrated gigabit ethernet controller needs a firmware file.
	  Select this if you are going to use the PCH integrated controller
	  and have the firmware.

config GBE_BIN_PATH
	string "Path to gigabit ethernet firmware"
	depends on HAVE_GBE_BIN
	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/gbe.bin"

config HAVE_ME_BIN
	bool "Add Intel Management Engine firmware"
	default y
	help
	  The Intel processor in the selected system requires a special firmware
	  for an integrated controller called Management Engine (ME). The ME
	  firmware might be provided in coreboot's 3rdparty/blobs repository. If
	  not and if you don't have the firmware elsewhere, you can still
	  build coreboot without it. In this case however, you'll have to make
	  sure that you don't overwrite your ME firmware on your flash ROM.

config ME_BIN_PATH
	string "Path to management engine firmware"
	depends on HAVE_ME_BIN
	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"

config LOCK_MANAGEMENT_ENGINE
	bool "Lock Management Engine section"
	depends on !BUILD_WITH_FAKE_IFD
	default n
	help
	  The Intel Management Engine supports preventing write accesses
	  from the host to the Management Engine section in the firmware
	  descriptor. If the ME section is locked, it can only be overwritten
	  with an external SPI flash programmer. You will want this if you
	  want to increase security of your ROM image once you are sure
	  that the ME firmware is no longer going to change.

	  If unsure, say N.

endif

if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 || SOUTHBRIDGE_INTEL_IBEXPEAK

choice
	prompt "Flash ROM locking on S3 resume"
	default LOCK_SPI_ON_RESUME_NONE

config LOCK_SPI_ON_RESUME_NONE
	bool "Don't lock ROM sections on S3 resume"

config LOCK_SPI_ON_RESUME_RO
	bool "Lock all flash ROM sections on S3 resume"
	help
	  If the flash ROM shall be protected against write accesses from the
	  operating system (OS), the locking procedure has to be repeated after
	  each resume from S3. Select this if you never want to update the flash
	  ROM from within your OS. Notice: Even with this option, the write lock
	  has still to be enabled on the normal boot path (e.g. by the payload).

config LOCK_SPI_ON_RESUME_NO_ACCESS
	bool "Lock and disable reads all flash ROM sections on S3 resume"
	help
	  If the flash ROM shall be protected against all accesses from the
	  operating system (OS), the locking procedure has to be repeated after
	  each resume from S3. Select this if you never want to update the flash
	  ROM from within your OS. Notice: Even with this option, the lock
	  has still to be enabled on the normal boot path (e.g. by the payload).

endchoice

endif