Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2011 Google Inc. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 15 | |
| 16 | config SOUTHBRIDGE_INTEL_BD82X6X |
| 17 | bool |
| 18 | |
| 19 | config SOUTHBRIDGE_INTEL_C216 |
| 20 | bool |
| 21 | |
| 22 | if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 |
| 23 | |
| 24 | config SOUTH_BRIDGE_OPTIONS # dummy |
| 25 | def_bool y |
Aaron Durbin | 340898f | 2016-07-13 23:22:28 -0500 | [diff] [blame] | 26 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Kyösti Mälkki | 71216c9 | 2013-07-28 23:39:37 +0300 | [diff] [blame] | 27 | select SOUTHBRIDGE_INTEL_COMMON |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame^] | 28 | select SOUTHBRIDGE_INTEL_COMMON_SMBUS |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 29 | select IOAPIC |
| 30 | select HAVE_HARD_RESET |
Kyösti Mälkki | 545b30d | 2013-06-13 13:51:14 +0300 | [diff] [blame] | 31 | select HAVE_USBDEBUG_OPTIONS |
Stefan Reinauer | 431a816 | 2012-11-13 13:01:31 -0800 | [diff] [blame] | 32 | select HAVE_SMI_HANDLER |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 33 | select USE_WATCHDOG_ON_BOOT |
| 34 | select PCIEXP_ASPM |
| 35 | select PCIEXP_COMMON_CLOCK |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 36 | select SPI_FLASH |
Vladimir Serbinenko | 5b044ae | 2014-10-25 15:20:55 +0200 | [diff] [blame] | 37 | select COMMON_FADT |
Alexander Couzens | 7bf47ee | 2015-04-16 02:00:21 +0200 | [diff] [blame] | 38 | select ACPI_SATA_GENERATOR |
Martin Roth | 3fda3c2 | 2015-07-09 21:02:26 -0600 | [diff] [blame] | 39 | select HAVE_INTEL_FIRMWARE |
Patrick Rudolph | e8e66f4 | 2016-02-06 17:42:42 +0100 | [diff] [blame] | 40 | select SOUTHBRIDGE_INTEL_COMMON_GPIO |
Aaron Durbin | 16246ea | 2016-08-05 21:23:37 -0500 | [diff] [blame] | 41 | select RTC |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 42 | |
| 43 | config EHCI_BAR |
| 44 | hex |
| 45 | default 0xfef00000 |
| 46 | |
Vladimir Serbinenko | 6a7aeb3 | 2014-01-05 11:37:32 +0100 | [diff] [blame] | 47 | config DRAM_RESET_GATE_GPIO |
| 48 | int |
| 49 | default 60 |
| 50 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 51 | config BOOTBLOCK_SOUTHBRIDGE_INIT |
| 52 | string |
| 53 | default "southbridge/intel/bd82x6x/bootblock.c" |
| 54 | |
| 55 | config SERIRQ_CONTINUOUS_MODE |
| 56 | bool |
| 57 | default n |
| 58 | help |
| 59 | If you set this option to y, the serial IRQ machine will be |
| 60 | operated in continuous mode. |
| 61 | |
Patrick Georgi | 9aeb694 | 2012-10-05 21:54:38 +0200 | [diff] [blame] | 62 | config HPET_MIN_TICKS |
| 63 | hex |
| 64 | default 0x80 |
| 65 | |
Nico Huber | a15cd66 | 2013-06-19 16:16:05 +0200 | [diff] [blame] | 66 | config HAVE_IFD_BIN |
Martin Roth | 3fda3c2 | 2015-07-09 21:02:26 -0600 | [diff] [blame] | 67 | def_bool y |
Nico Huber | a15cd66 | 2013-06-19 16:16:05 +0200 | [diff] [blame] | 68 | |
| 69 | config BUILD_WITH_FAKE_IFD |
Martin Roth | 3fda3c2 | 2015-07-09 21:02:26 -0600 | [diff] [blame] | 70 | def_bool !HAVE_IFD_BIN |
Stefan Reinauer | 7004b7c | 2012-10-31 17:30:13 -0700 | [diff] [blame] | 71 | |
Vladimir Serbinenko | d3b194e | 2015-05-12 12:39:53 +0200 | [diff] [blame] | 72 | endif |
| 73 | |
| 74 | if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 || SOUTHBRIDGE_INTEL_IBEXPEAK |
| 75 | |
| 76 | choice |
| 77 | prompt "Flash ROM locking on S3 resume" |
| 78 | default LOCK_SPI_ON_RESUME_NONE |
| 79 | |
| 80 | config LOCK_SPI_ON_RESUME_NONE |
| 81 | bool "Don't lock ROM sections on S3 resume" |
| 82 | |
| 83 | config LOCK_SPI_ON_RESUME_RO |
Nico Huber | d1fb564 | 2013-07-01 16:02:36 +0200 | [diff] [blame] | 84 | bool "Lock all flash ROM sections on S3 resume" |
Nico Huber | d1fb564 | 2013-07-01 16:02:36 +0200 | [diff] [blame] | 85 | help |
| 86 | If the flash ROM shall be protected against write accesses from the |
| 87 | operating system (OS), the locking procedure has to be repeated after |
| 88 | each resume from S3. Select this if you never want to update the flash |
| 89 | ROM from within your OS. Notice: Even with this option, the write lock |
| 90 | has still to be enabled on the normal boot path (e.g. by the payload). |
| 91 | |
Vladimir Serbinenko | d3b194e | 2015-05-12 12:39:53 +0200 | [diff] [blame] | 92 | config LOCK_SPI_ON_RESUME_NO_ACCESS |
| 93 | bool "Lock and disable reads all flash ROM sections on S3 resume" |
| 94 | help |
| 95 | If the flash ROM shall be protected against all accesses from the |
| 96 | operating system (OS), the locking procedure has to be repeated after |
| 97 | each resume from S3. Select this if you never want to update the flash |
| 98 | ROM from within your OS. Notice: Even with this option, the lock |
| 99 | has still to be enabled on the normal boot path (e.g. by the payload). |
| 100 | |
| 101 | endchoice |
| 102 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 103 | endif |