blob: a6009cd81f9d207ef903a8143afe51d3e5940b6e [file] [log] [blame]
Stefan Reinauer8e073822012-04-04 00:07:22 +02001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2011 Google Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
Stefan Reinauer8e073822012-04-04 00:07:22 +020015
16config SOUTHBRIDGE_INTEL_BD82X6X
17 bool
18
19config SOUTHBRIDGE_INTEL_C216
20 bool
21
22if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216
23
24config SOUTH_BRIDGE_OPTIONS # dummy
25 def_bool y
Aaron Durbin340898f2016-07-13 23:22:28 -050026 select ACPI_INTEL_HARDWARE_SLEEP_VALUES
Kyösti Mälkki71216c92013-07-28 23:39:37 +030027 select SOUTHBRIDGE_INTEL_COMMON
Stefan Reinauer8e073822012-04-04 00:07:22 +020028 select IOAPIC
29 select HAVE_HARD_RESET
Kyösti Mälkki545b30d2013-06-13 13:51:14 +030030 select HAVE_USBDEBUG_OPTIONS
Stefan Reinauer431a8162012-11-13 13:01:31 -080031 select HAVE_SMI_HANDLER
Stefan Reinauer8e073822012-04-04 00:07:22 +020032 select USE_WATCHDOG_ON_BOOT
33 select PCIEXP_ASPM
34 select PCIEXP_COMMON_CLOCK
Stefan Reinauer1c56d9b2012-05-10 11:27:32 -070035 select SPI_FLASH
Vladimir Serbinenko5b044ae2014-10-25 15:20:55 +020036 select COMMON_FADT
Alexander Couzens7bf47ee2015-04-16 02:00:21 +020037 select ACPI_SATA_GENERATOR
Martin Roth3fda3c22015-07-09 21:02:26 -060038 select HAVE_INTEL_FIRMWARE
Patrick Rudolphe8e66f42016-02-06 17:42:42 +010039 select SOUTHBRIDGE_INTEL_COMMON_GPIO
Stefan Reinauer8e073822012-04-04 00:07:22 +020040
41config EHCI_BAR
42 hex
43 default 0xfef00000
44
Vladimir Serbinenko6a7aeb32014-01-05 11:37:32 +010045config DRAM_RESET_GATE_GPIO
46 int
47 default 60
48
Stefan Reinauer8e073822012-04-04 00:07:22 +020049config BOOTBLOCK_SOUTHBRIDGE_INIT
50 string
51 default "southbridge/intel/bd82x6x/bootblock.c"
52
53config SERIRQ_CONTINUOUS_MODE
54 bool
55 default n
56 help
57 If you set this option to y, the serial IRQ machine will be
58 operated in continuous mode.
59
Patrick Georgi9aeb6942012-10-05 21:54:38 +020060config HPET_MIN_TICKS
61 hex
62 default 0x80
63
Nico Hubera15cd662013-06-19 16:16:05 +020064config HAVE_IFD_BIN
Martin Roth3fda3c22015-07-09 21:02:26 -060065 def_bool y
Nico Hubera15cd662013-06-19 16:16:05 +020066
67config BUILD_WITH_FAKE_IFD
Martin Roth3fda3c22015-07-09 21:02:26 -060068 def_bool !HAVE_IFD_BIN
Stefan Reinauer7004b7c2012-10-31 17:30:13 -070069
Vladimir Serbinenkod3b194e2015-05-12 12:39:53 +020070endif
71
72if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 || SOUTHBRIDGE_INTEL_IBEXPEAK
73
74choice
75 prompt "Flash ROM locking on S3 resume"
76 default LOCK_SPI_ON_RESUME_NONE
77
78config LOCK_SPI_ON_RESUME_NONE
79 bool "Don't lock ROM sections on S3 resume"
80
81config LOCK_SPI_ON_RESUME_RO
Nico Huberd1fb5642013-07-01 16:02:36 +020082 bool "Lock all flash ROM sections on S3 resume"
Nico Huberd1fb5642013-07-01 16:02:36 +020083 help
84 If the flash ROM shall be protected against write accesses from the
85 operating system (OS), the locking procedure has to be repeated after
86 each resume from S3. Select this if you never want to update the flash
87 ROM from within your OS. Notice: Even with this option, the write lock
88 has still to be enabled on the normal boot path (e.g. by the payload).
89
Vladimir Serbinenkod3b194e2015-05-12 12:39:53 +020090config LOCK_SPI_ON_RESUME_NO_ACCESS
91 bool "Lock and disable reads all flash ROM sections on S3 resume"
92 help
93 If the flash ROM shall be protected against all accesses from the
94 operating system (OS), the locking procedure has to be repeated after
95 each resume from S3. Select this if you never want to update the flash
96 ROM from within your OS. Notice: Even with this option, the lock
97 has still to be enabled on the normal boot path (e.g. by the payload).
98
99endchoice
100
Stefan Reinauer8e073822012-04-04 00:07:22 +0200101endif