blob: e5a6270469ef68dc73a18d6f761646a41603ed4e [file] [log] [blame]
Stefan Reinauer8e073822012-04-04 00:07:22 +02001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2011 Google Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15## You should have received a copy of the GNU General Public License
16## along with this program; if not, write to the Free Software
17## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18##
19
20config SOUTHBRIDGE_INTEL_BD82X6X
21 bool
22
23config SOUTHBRIDGE_INTEL_C216
24 bool
25
26if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216
27
28config SOUTH_BRIDGE_OPTIONS # dummy
29 def_bool y
30 select IOAPIC
31 select HAVE_HARD_RESET
32 select HAVE_USBDEBUG
Stefan Reinauer431a8162012-11-13 13:01:31 -080033 select HAVE_SMI_HANDLER
Stefan Reinauer8e073822012-04-04 00:07:22 +020034 select USE_WATCHDOG_ON_BOOT
35 select PCIEXP_ASPM
36 select PCIEXP_COMMON_CLOCK
Stefan Reinauer1c56d9b2012-05-10 11:27:32 -070037 select SPI_FLASH
Stefan Reinauer8e073822012-04-04 00:07:22 +020038
39config EHCI_BAR
40 hex
41 default 0xfef00000
42
43config EHCI_DEBUG_OFFSET
44 hex
45 default 0xa0
46
47config BOOTBLOCK_SOUTHBRIDGE_INIT
48 string
49 default "southbridge/intel/bd82x6x/bootblock.c"
50
51config SERIRQ_CONTINUOUS_MODE
52 bool
53 default n
54 help
55 If you set this option to y, the serial IRQ machine will be
56 operated in continuous mode.
57
Patrick Georgi9aeb6942012-10-05 21:54:38 +020058config HPET_MIN_TICKS
59 hex
60 default 0x80
61
Stefan Reinauer7004b7c2012-10-31 17:30:13 -070062config LOCK_MANAGEMENT_ENGINE
63 bool "Lock Management Engine section"
64 default n
65 help
66 The Intel Management Engine supports preventing write accesses
67 from the host to the Management Engine section in the firmware
68 descriptor. If the ME section is locked, it can only be overwritten
69 with an external SPI flash programmer. You will want this if you
70 want to increase security of your ROM image once you are sure
71 that the ME firmware is no longer going to change.
72
73 If unsure, say N.
74
Stefan Reinauer8e073822012-04-04 00:07:22 +020075endif