blob: c2720ef4c7a9208ee5d245f94381995ccefd1500 [file] [log] [blame]
Stefan Reinauer8e073822012-04-04 00:07:22 +02001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2011 Google Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15## You should have received a copy of the GNU General Public License
16## along with this program; if not, write to the Free Software
Paul Menzela46a7122013-02-23 18:37:27 +010017## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Stefan Reinauer8e073822012-04-04 00:07:22 +020018##
19
20config SOUTHBRIDGE_INTEL_BD82X6X
21 bool
22
23config SOUTHBRIDGE_INTEL_C216
24 bool
25
26if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216
27
28config SOUTH_BRIDGE_OPTIONS # dummy
29 def_bool y
Kyösti Mälkki71216c92013-07-28 23:39:37 +030030 select SOUTHBRIDGE_INTEL_COMMON
Stefan Reinauer8e073822012-04-04 00:07:22 +020031 select IOAPIC
32 select HAVE_HARD_RESET
Kyösti Mälkki545b30d2013-06-13 13:51:14 +030033 select HAVE_USBDEBUG_OPTIONS
Stefan Reinauer431a8162012-11-13 13:01:31 -080034 select HAVE_SMI_HANDLER
Stefan Reinauer8e073822012-04-04 00:07:22 +020035 select USE_WATCHDOG_ON_BOOT
36 select PCIEXP_ASPM
37 select PCIEXP_COMMON_CLOCK
Stefan Reinauer1c56d9b2012-05-10 11:27:32 -070038 select SPI_FLASH
Stefan Reinauer8e073822012-04-04 00:07:22 +020039
40config EHCI_BAR
41 hex
42 default 0xfef00000
43
44config EHCI_DEBUG_OFFSET
45 hex
46 default 0xa0
47
48config BOOTBLOCK_SOUTHBRIDGE_INIT
49 string
50 default "southbridge/intel/bd82x6x/bootblock.c"
51
52config SERIRQ_CONTINUOUS_MODE
53 bool
54 default n
55 help
56 If you set this option to y, the serial IRQ machine will be
57 operated in continuous mode.
58
Patrick Georgi9aeb6942012-10-05 21:54:38 +020059config HPET_MIN_TICKS
60 hex
61 default 0x80
62
Nico Hubera15cd662013-06-19 16:16:05 +020063config HAVE_IFD_BIN
64 bool
65 default y
66
67config BUILD_WITH_FAKE_IFD
68 bool "Build with a fake IFD"
69 default y if !HAVE_IFD_BIN
70 help
71 If you don't have an Intel Firmware Descriptor (ifd.bin) for your
72 board, you can select this option and coreboot will build without it.
73 Though, the resulting coreboot.rom will not contain all parts required
74 to get coreboot running on your board. You can however write only the
75 BIOS section to your board's flash ROM and keep the other sections
76 untouched. Unfortunately the current version of flashrom doesn't
77 support this yet. But there is a patch pending [1].
78
79 WARNING: Never write a complete coreboot.rom to your flash ROM if it
80 was built with a fake IFD. It just won't work.
81
82 [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
83
84config IFD_BIOS_SECTION
85 depends on BUILD_WITH_FAKE_IFD
86 string
87 default ""
88
89config IFD_ME_SECTION
90 depends on BUILD_WITH_FAKE_IFD
91 string
92 default ""
93
94config IFD_GBE_SECTION
95 depends on BUILD_WITH_FAKE_IFD
96 string
97 default ""
98
99config IFD_PLATFORM_SECTION
100 depends on BUILD_WITH_FAKE_IFD
101 string
102 default ""
103
104config IFD_BIN_PATH
105 string "Path to intel firmware descriptor"
106 depends on !BUILD_WITH_FAKE_IFD
107 default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin"
108
Nico Huberea6d6e8c2013-05-14 15:14:08 +0200109config HAVE_GBE_BIN
110 bool "Add gigabit ethernet firmware"
111 default n
112 help
113 The integrated gigabit ethernet controller needs a firmware file.
114 Select this if you are going to use the PCH integrated controller
115 and have the firmware.
116
117config GBE_BIN_PATH
118 string "Path to gigabit ethernet firmware"
119 depends on HAVE_GBE_BIN
120 default "3rdparty/mainboard/$(MAINBOARDDIR)/gbe.bin"
121
Nico Huber99fd30e2013-06-19 15:57:34 +0200122config HAVE_ME_BIN
123 bool "Add Intel Management Engine firmware"
124 default y
125 help
126 The Intel processor in the selected system requires a special firmware
127 for an integrated controller called Management Engine (ME). The ME
128 firmware might be provided in coreboot's 3rdparty repository. If
129 not and if you don't have the firmware elsewhere, you can still
130 build coreboot without it. In this case however, you'll have to make
131 sure that you don't overwrite your ME firmware on your flash ROM.
132
Patrick Georgi3cc151e2013-06-13 15:07:02 +0200133config ME_BIN_PATH
134 string "Path to management engine firmware"
Nico Huber99fd30e2013-06-19 15:57:34 +0200135 depends on HAVE_ME_BIN
Patrick Georgi3cc151e2013-06-13 15:07:02 +0200136 default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin"
137
Stefan Reinauer7004b7c2012-10-31 17:30:13 -0700138config LOCK_MANAGEMENT_ENGINE
139 bool "Lock Management Engine section"
Nico Hubera15cd662013-06-19 16:16:05 +0200140 depends on !BUILD_WITH_FAKE_IFD
Stefan Reinauer7004b7c2012-10-31 17:30:13 -0700141 default n
142 help
143 The Intel Management Engine supports preventing write accesses
144 from the host to the Management Engine section in the firmware
145 descriptor. If the ME section is locked, it can only be overwritten
146 with an external SPI flash programmer. You will want this if you
147 want to increase security of your ROM image once you are sure
148 that the ME firmware is no longer going to change.
149
150 If unsure, say N.
151
Nico Huberd1fb5642013-07-01 16:02:36 +0200152config LOCK_SPI_ON_RESUME
153 bool "Lock all flash ROM sections on S3 resume"
154 default n
155 help
156 If the flash ROM shall be protected against write accesses from the
157 operating system (OS), the locking procedure has to be repeated after
158 each resume from S3. Select this if you never want to update the flash
159 ROM from within your OS. Notice: Even with this option, the write lock
160 has still to be enabled on the normal boot path (e.g. by the payload).
161
Stefan Reinauer8e073822012-04-04 00:07:22 +0200162endif