blob: 1396a6395b83febfd935f445360926fddeb2e73f [file] [log] [blame]
Stefan Reinauer8e073822012-04-04 00:07:22 +02001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2011 Google Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
Stefan Reinauer8e073822012-04-04 00:07:22 +020015
16config SOUTHBRIDGE_INTEL_BD82X6X
17 bool
18
19config SOUTHBRIDGE_INTEL_C216
20 bool
21
22if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216
23
24config SOUTH_BRIDGE_OPTIONS # dummy
25 def_bool y
Aaron Durbin340898f2016-07-13 23:22:28 -050026 select ACPI_INTEL_HARDWARE_SLEEP_VALUES
Kyösti Mälkki71216c92013-07-28 23:39:37 +030027 select SOUTHBRIDGE_INTEL_COMMON
Tristan Corrick63626b12018-11-30 22:53:50 +130028 select SOUTHBRIDGE_INTEL_COMMON_FINALIZE
Tobias Diedrich7f5efd92017-12-14 00:29:01 +010029 select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
Arthur Heymans16fe7902017-04-12 17:01:31 +020030 select SOUTHBRIDGE_INTEL_COMMON_SMBUS
Arthur Heymansbddef0d2017-09-25 12:21:07 +020031 select SOUTHBRIDGE_INTEL_COMMON_SPI
Stefan Reinauer8e073822012-04-04 00:07:22 +020032 select IOAPIC
Kyösti Mälkki545b30d2013-06-13 13:51:14 +030033 select HAVE_USBDEBUG_OPTIONS
Stefan Reinauer431a8162012-11-13 13:01:31 -080034 select HAVE_SMI_HANDLER
Stefan Reinauer8e073822012-04-04 00:07:22 +020035 select USE_WATCHDOG_ON_BOOT
36 select PCIEXP_ASPM
37 select PCIEXP_COMMON_CLOCK
Vladimir Serbinenko5b044ae2014-10-25 15:20:55 +020038 select COMMON_FADT
Alexander Couzens7bf47ee2015-04-16 02:00:21 +020039 select ACPI_SATA_GENERATOR
Stefan Tauneref8b9572018-09-06 00:34:28 +020040 select INTEL_DESCRIPTOR_MODE_CAPABLE
Patrick Rudolphe8e66f42016-02-06 17:42:42 +010041 select SOUTHBRIDGE_INTEL_COMMON_GPIO
Aaron Durbin16246ea2016-08-05 21:23:37 -050042 select RTC
Bill XIEd533b162017-08-22 16:26:22 +080043 select HAVE_INTEL_CHIPSET_LOCKDOWN
Arthur Heymansa0508172018-01-25 11:30:22 +010044 select SOUTHBRIDGE_INTEL_COMMON_SMM
Tristan Corrick167a5122018-10-31 02:28:32 +130045 select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
Stefan Reinauer8e073822012-04-04 00:07:22 +020046
47config EHCI_BAR
48 hex
49 default 0xfef00000
50
Vladimir Serbinenko6a7aeb32014-01-05 11:37:32 +010051config DRAM_RESET_GATE_GPIO
52 int
53 default 60
54
Stefan Reinauer8e073822012-04-04 00:07:22 +020055config BOOTBLOCK_SOUTHBRIDGE_INIT
56 string
57 default "southbridge/intel/bd82x6x/bootblock.c"
58
59config SERIRQ_CONTINUOUS_MODE
60 bool
61 default n
62 help
63 If you set this option to y, the serial IRQ machine will be
64 operated in continuous mode.
65
Patrick Georgi9aeb6942012-10-05 21:54:38 +020066config HPET_MIN_TICKS
67 hex
68 default 0x80
69
Vladimir Serbinenkod3b194e2015-05-12 12:39:53 +020070endif