Ravi Sarawadi | ebb2d3c | 2019-12-19 23:01:48 -0800 | [diff] [blame] | 1 | chip soc/intel/tigerlake |
| 2 | |
Shaunak Saha | d72cca0 | 2020-03-25 11:42:12 -0700 | [diff] [blame] | 3 | # GPE configuration |
| 4 | # Note that GPE events called out in ASL code rely on this |
| 5 | # route. i.e. If this route changes then the affected GPE |
| 6 | # offset bits also need to be changed. |
| 7 | register "pmc_gpe0_dw0" = "GPP_B" |
Shaunak Saha | b449b9c | 2020-08-23 21:35:21 -0700 | [diff] [blame] | 8 | register "pmc_gpe0_dw1" = "GPP_C" |
| 9 | register "pmc_gpe0_dw2" = "GPP_D" |
Shaunak Saha | d72cca0 | 2020-03-25 11:42:12 -0700 | [diff] [blame] | 10 | |
Ravi Sarawadi | 97e1e3e | 2019-12-24 15:54:56 -0800 | [diff] [blame] | 11 | # FSP configuration |
Shreesh Chhabbi | c7fe0bd | 2020-07-07 18:25:45 -0700 | [diff] [blame] | 12 | register "SaGv" = "SaGv_Enabled" |
Ravi Sarawadi | 97e1e3e | 2019-12-24 15:54:56 -0800 | [diff] [blame] | 13 | |
Cliff Huang | 3663fb3 | 2021-02-09 15:16:18 -0800 | [diff] [blame] | 14 | # CNVi BT enable/disable |
| 15 | register "CnviBtCore" = "true" |
| 16 | |
Ravi Sarawadi | 97e1e3e | 2019-12-24 15:54:56 -0800 | [diff] [blame] | 17 | register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 |
Bora Guvendik | 7377cda | 2020-08-28 10:50:47 -0700 | [diff] [blame] | 18 | register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN |
Ravi Sarawadi | 97e1e3e | 2019-12-24 15:54:56 -0800 | [diff] [blame] | 19 | register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # M.2 Bluetooth |
| 20 | register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 |
| 21 | register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 |
| 22 | register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 |
| 23 | register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-C Port4 |
| 24 | register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 |
| 25 | register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB2 Type A port3 |
| 26 | register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # USB2 Type A port4 |
| 27 | |
| 28 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 |
| 29 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 |
Ravi Sarawadi | 97e1e3e | 2019-12-24 15:54:56 -0800 | [diff] [blame] | 30 | |
Angel Pons | e16692e | 2020-08-03 12:54:48 +0200 | [diff] [blame] | 31 | # CPU replacement check |
| 32 | register "CpuReplacementCheck" = "1" |
Jamie Ryu | ef079c8 | 2020-06-24 15:55:10 -0700 | [diff] [blame] | 33 | |
Ravi Sarawadi | 97e1e3e | 2019-12-24 15:54:56 -0800 | [diff] [blame] | 34 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 35 | register "gen1_dec" = "0x00fc0801" |
| 36 | register "gen2_dec" = "0x000c0201" |
| 37 | # EC memory map range is 0x900-0x9ff |
| 38 | register "gen3_dec" = "0x00fc0901" |
| 39 | |
Michael Niewöhner | 45b6080 | 2022-01-08 20:47:11 +0100 | [diff] [blame] | 40 | register "PcieRpSlotImplemented[2]" = "1" |
| 41 | register "PcieRpSlotImplemented[3]" = "1" |
| 42 | register "PcieRpSlotImplemented[8]" = "1" |
| 43 | register "PcieRpSlotImplemented[10]" = "1" |
Ravi Sarawadi | 97e1e3e | 2019-12-24 15:54:56 -0800 | [diff] [blame] | 44 | |
Wonkyu Kim | 53ac68e | 2020-04-07 23:37:11 -0700 | [diff] [blame] | 45 | # Enable RP LTR |
| 46 | register "PcieRpLtrEnable[2]" = "1" |
| 47 | register "PcieRpLtrEnable[3]" = "1" |
| 48 | register "PcieRpLtrEnable[8]" = "1" |
| 49 | register "PcieRpLtrEnable[10]" = "1" |
| 50 | |
Wonkyu Kim | f787e87 | 2020-03-03 01:58:17 -0800 | [diff] [blame] | 51 | # Hybrid storage mode |
| 52 | register "HybridStorageMode" = "1" |
| 53 | |
Ravi Sarawadi | 97e1e3e | 2019-12-24 15:54:56 -0800 | [diff] [blame] | 54 | register "PcieClkSrcClkReq[1]" = "1" |
| 55 | register "PcieClkSrcClkReq[2]" = "2" |
| 56 | register "PcieClkSrcClkReq[3]" = "3" |
| 57 | |
| 58 | register "PcieClkSrcUsage[1]" = "0x2" |
| 59 | register "PcieClkSrcUsage[2]" = "0x3" |
| 60 | register "PcieClkSrcUsage[3]" = "0x8" |
| 61 | |
Wonkyu Kim | 46cef44 | 2020-01-23 00:12:46 -0800 | [diff] [blame] | 62 | # enabling EDP in PortA |
Angel Pons | da4e1d7 | 2022-05-04 17:08:11 +0200 | [diff] [blame] | 63 | register "DdiPortAConfig" = "DDI_PORT_CFG_EDP" |
Wonkyu Kim | 46cef44 | 2020-01-23 00:12:46 -0800 | [diff] [blame] | 64 | |
Wonkyu Kim | 34944be | 2020-03-02 22:18:26 -0800 | [diff] [blame] | 65 | register "DdiPortBHpd" = "1" |
Wonkyu Kim | 46cef44 | 2020-01-23 00:12:46 -0800 | [diff] [blame] | 66 | register "DdiPort1Hpd" = "1" |
| 67 | register "DdiPort1Ddc" = "1" |
| 68 | |
Ravi Sarawadi | 97e1e3e | 2019-12-24 15:54:56 -0800 | [diff] [blame] | 69 | register "SerialIoI2cMode" = "{ |
| 70 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 71 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 72 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
| 73 | [PchSerialIoIndexI2C3] = PchSerialIoPci, |
| 74 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| 75 | [PchSerialIoIndexI2C5] = PchSerialIoPci, |
| 76 | }" |
| 77 | |
| 78 | register "SerialIoGSpiMode" = "{ |
| 79 | [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, |
Shaunak Saha | b449b9c | 2020-08-23 21:35:21 -0700 | [diff] [blame] | 80 | [PchSerialIoIndexGSPI1] = PchSerialIoPci, |
Ravi Sarawadi | 97e1e3e | 2019-12-24 15:54:56 -0800 | [diff] [blame] | 81 | [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, |
| 82 | [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, |
| 83 | }" |
| 84 | |
| 85 | register "SerialIoGSpiCsMode" = "{ |
| 86 | [PchSerialIoIndexGSPI0] = 0, |
Shaunak Saha | b449b9c | 2020-08-23 21:35:21 -0700 | [diff] [blame] | 87 | [PchSerialIoIndexGSPI1] = 1, |
Ravi Sarawadi | 97e1e3e | 2019-12-24 15:54:56 -0800 | [diff] [blame] | 88 | [PchSerialIoIndexGSPI2] = 0, |
| 89 | [PchSerialIoIndexGSPI3] = 0, |
| 90 | }" |
| 91 | |
| 92 | register "SerialIoGSpiCsState" = "{ |
| 93 | [PchSerialIoIndexGSPI0] = 0, |
| 94 | [PchSerialIoIndexGSPI1] = 0, |
| 95 | [PchSerialIoIndexGSPI2] = 0, |
| 96 | [PchSerialIoIndexGSPI3] = 0, |
| 97 | }" |
| 98 | |
| 99 | register "SerialIoUartMode" = "{ |
| 100 | [PchSerialIoIndexUART0] = PchSerialIoDisabled, |
| 101 | [PchSerialIoIndexUART1] = PchSerialIoDisabled, |
| 102 | [PchSerialIoIndexUART2] = PchSerialIoPci, |
| 103 | }" |
Ravi Sarawadi | ebb2d3c | 2019-12-19 23:01:48 -0800 | [diff] [blame] | 104 | |
John Zhao | b1c53fc | 2020-05-13 16:27:03 -0700 | [diff] [blame] | 105 | # TCSS USB3 |
| 106 | register "TcssXhciEn" = "1" |
| 107 | register "TcssAuxOri" = "0" |
| 108 | |
John Zhao | 23d3ad0 | 2020-06-30 17:36:24 -0700 | [diff] [blame] | 109 | # Enable S0ix |
| 110 | register "s0ix_enable" = "1" |
| 111 | |
Sumeet R Pawnikar | 06b35e5 | 2020-09-09 23:44:06 +0530 | [diff] [blame] | 112 | # Enable DPTF |
| 113 | register "dptf_enable" = "1" |
| 114 | |
Sumeet R Pawnikar | 06b35e5 | 2020-09-09 23:44:06 +0530 | [diff] [blame] | 115 | # Add PL1 and PL2 values |
| 116 | register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ |
| 117 | .tdp_pl1_override = 15, |
| 118 | .tdp_pl2_override = 38, |
| 119 | .tdp_pl4 = 71, |
| 120 | }" |
| 121 | register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ |
| 122 | .tdp_pl1_override = 15, |
| 123 | .tdp_pl2_override = 60, |
| 124 | .tdp_pl4 = 105, |
| 125 | }" |
| 126 | |
Srinidhi N Kaushik | b2ecc57 | 2020-01-24 10:43:48 -0800 | [diff] [blame] | 127 | #HD Audio |
| 128 | register "PchHdaDspEnable" = "1" |
Srinidhi N Kaushik | b2ecc57 | 2020-01-24 10:43:48 -0800 | [diff] [blame] | 129 | register "PchHdaAudioLinkDmicEnable[0]" = "1" |
| 130 | register "PchHdaAudioLinkDmicEnable[1]" = "1" |
| 131 | register "PchHdaAudioLinkSspEnable[0]" = "1" |
Srinidhi N Kaushik | 6975e07 | 2020-03-12 01:22:01 -0700 | [diff] [blame] | 132 | register "PchHdaAudioLinkSspEnable[2]" = "1" |
| 133 | register "PchHdaAudioLinkSndwEnable[0]" = "1" |
Srinidhi N Kaushik | b2ecc57 | 2020-01-24 10:43:48 -0800 | [diff] [blame] | 134 | |
Wonkyu Kim | 5c27182 | 2020-04-03 00:42:22 -0700 | [diff] [blame] | 135 | # Intel Common SoC Config |
| 136 | register "common_soc_config" = "{ |
Shaunak Saha | b449b9c | 2020-08-23 21:35:21 -0700 | [diff] [blame] | 137 | .gspi[1] = { |
| 138 | .speed_mhz = 1, |
| 139 | .early_init = 1, |
| 140 | }, |
Wonkyu Kim | 5c27182 | 2020-04-03 00:42:22 -0700 | [diff] [blame] | 141 | .i2c[0] = { |
| 142 | .speed = I2C_SPEED_FAST, |
| 143 | }, |
| 144 | .i2c[1] = { |
| 145 | .speed = I2C_SPEED_FAST, |
| 146 | }, |
| 147 | .i2c[2] = { |
| 148 | .speed = I2C_SPEED_FAST, |
Angel Pons | e16692e | 2020-08-03 12:54:48 +0200 | [diff] [blame] | 149 | }, |
Wonkyu Kim | 5c27182 | 2020-04-03 00:42:22 -0700 | [diff] [blame] | 150 | .i2c[3] = { |
| 151 | .speed = I2C_SPEED_FAST, |
| 152 | }, |
| 153 | .i2c[5] = { |
| 154 | .speed = I2C_SPEED_FAST, |
| 155 | }, |
| 156 | }" |
| 157 | |
Ravi Sarawadi | ebb2d3c | 2019-12-19 23:01:48 -0800 | [diff] [blame] | 158 | device domain 0 on |
Felix Singer | f13284c | 2024-06-27 21:09:11 +0200 | [diff] [blame] | 159 | device ref system_agent on end |
| 160 | device ref igpu on end |
| 161 | device ref dptf on |
Sumeet R Pawnikar | 06b35e5 | 2020-09-09 23:44:06 +0530 | [diff] [blame] | 162 | # Default DPTF Policy for all tglrvp_up3 boards if not overridden |
| 163 | chip drivers/intel/dptf |
| 164 | register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)" |
| 165 | register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" |
| 166 | |
| 167 | # Power Limits Control |
| 168 | register "controls.power_limits.pl1" = "{ |
| 169 | .min_power = 3000, |
| 170 | .max_power = 15000, |
| 171 | .time_window_min = 28 * MSECS_PER_SEC, |
| 172 | .time_window_max = 32 * MSECS_PER_SEC, |
| 173 | .granularity = 200,}" |
| 174 | register "controls.power_limits.pl2" = "{ |
Sumeet Pawnikar | 681a59d | 2021-07-05 17:15:51 +0530 | [diff] [blame] | 175 | .min_power = 60000, |
Sumeet R Pawnikar | 06b35e5 | 2020-09-09 23:44:06 +0530 | [diff] [blame] | 176 | .max_power = 60000, |
| 177 | .time_window_min = 28 * MSECS_PER_SEC, |
| 178 | .time_window_max = 32 * MSECS_PER_SEC, |
| 179 | .granularity = 1000,}" |
| 180 | device generic 0 on end |
| 181 | end |
Felix Singer | f13284c | 2024-06-27 21:09:11 +0200 | [diff] [blame] | 182 | end |
Sumeet R Pawnikar | 06b35e5 | 2020-09-09 23:44:06 +0530 | [diff] [blame] | 183 | |
Felix Singer | f13284c | 2024-06-27 21:09:11 +0200 | [diff] [blame] | 184 | device ref ipu on end |
| 185 | device ref peg on end |
| 186 | device ref tbt_pcie_rp0 on end |
| 187 | device ref tbt_pcie_rp1 on end |
| 188 | device ref tbt_pcie_rp2 on end |
| 189 | device ref tbt_pcie_rp3 on end |
| 190 | device ref gna off end |
| 191 | device ref npk off end |
| 192 | device ref crashlog off end |
| 193 | device ref north_xhci on end |
| 194 | device ref north_xdci on end |
| 195 | device ref tbt_dma0 on end |
| 196 | device ref tbt_dma1 on end |
| 197 | device ref vmd off end |
Ravi Sarawadi | ebb2d3c | 2019-12-19 23:01:48 -0800 | [diff] [blame] | 198 | |
Felix Singer | f13284c | 2024-06-27 21:09:11 +0200 | [diff] [blame] | 199 | device ref thc0 off end |
| 200 | device ref thc1 off end |
| 201 | device ref ish on |
li feng | 2395425 | 2020-03-12 16:38:34 -0700 | [diff] [blame] | 202 | chip drivers/intel/ish |
| 203 | register "firmware_name" = ""tglrvp_ish.bin"" |
| 204 | device generic 0 on end |
| 205 | end |
| 206 | end |
Felix Singer | f13284c | 2024-06-27 21:09:11 +0200 | [diff] [blame] | 207 | device ref gspi2 off end |
| 208 | device ref gspi3 off end |
| 209 | device ref south_xhci on end |
| 210 | device ref south_xdci on end |
| 211 | device ref shared_ram on end |
| 212 | device ref cnvi_wifi on |
Furquan Shaikh | edac4ef | 2020-10-09 08:50:14 -0700 | [diff] [blame] | 213 | chip drivers/wifi/generic |
| 214 | register "wake" = "GPE0_PME_B0" |
| 215 | device generic 0 on end |
| 216 | end |
Felix Singer | f13284c | 2024-06-27 21:09:11 +0200 | [diff] [blame] | 217 | end |
Srinidhi N Kaushik | dcd3d07 | 2020-03-05 00:41:14 -0800 | [diff] [blame] | 218 | |
Felix Singer | f13284c | 2024-06-27 21:09:11 +0200 | [diff] [blame] | 219 | device ref i2c0 on |
Shaunak Saha | 48b388f | 2020-05-27 22:48:57 -0700 | [diff] [blame] | 220 | chip drivers/i2c/generic |
| 221 | register "hid" = ""10EC1308"" |
| 222 | register "name" = ""RTAM"" |
| 223 | register "desc" = ""Realtek RT1308 Codec"" |
| 224 | device i2c 10 on end |
| 225 | end |
Srinidhi N Kaushik | b2ecc57 | 2020-01-24 10:43:48 -0800 | [diff] [blame] | 226 | chip drivers/i2c/max98373 |
| 227 | register "vmon_slot_no" = "4" |
| 228 | register "imon_slot_no" = "5" |
| 229 | register "uid" = "0" |
| 230 | register "desc" = ""RIGHT SPEAKER AMP"" |
| 231 | register "name" = ""MAXR"" |
| 232 | device i2c 31 on end |
| 233 | end |
| 234 | chip drivers/i2c/max98373 |
| 235 | register "vmon_slot_no" = "6" |
| 236 | register "imon_slot_no" = "7" |
| 237 | register "uid" = "1" |
| 238 | register "desc" = ""LEFT SPEAKER AMP"" |
| 239 | register "name" = ""MAXL"" |
| 240 | device i2c 32 on end |
| 241 | end |
| 242 | chip drivers/i2c/generic |
| 243 | register "hid" = ""10EC5682"" |
| 244 | register "name" = ""RT58"" |
| 245 | register "desc" = ""Realtek RT5682"" |
| 246 | register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_C12_IRQ)" |
| 247 | register "probed" = "1" |
| 248 | # Set the jd_src to RT5668_JD1 for jack detection |
| 249 | register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" |
| 250 | register "property_list[0].name" = ""realtek,jd-src"" |
| 251 | register "property_list[0].integer" = "1" |
| 252 | device i2c 1a on end |
| 253 | end |
Felix Singer | f13284c | 2024-06-27 21:09:11 +0200 | [diff] [blame] | 254 | end |
| 255 | device ref i2c1 on end |
| 256 | device ref i2c2 on end |
| 257 | device ref i2c3 on end |
| 258 | device ref heci1 on end |
| 259 | device ref heci2 off end |
| 260 | device ref csme1 off end |
| 261 | device ref csme2 off end |
| 262 | device ref heci3 off end |
| 263 | device ref heci4 off end |
Felix Singer | 8c1daf9 | 2024-06-27 23:25:32 +0200 | [diff] [blame] | 264 | device ref sata on |
| 265 | register "SataSalpSupport" = "1" |
| 266 | register "SataPortsEnable[0]" = "1" |
| 267 | register "SataPortsEnable[1]" = "1" |
| 268 | end |
Felix Singer | f13284c | 2024-06-27 21:09:11 +0200 | [diff] [blame] | 269 | device ref i2c4 off end |
| 270 | device ref i2c5 on end |
| 271 | device ref uart2 on end |
| 272 | device ref pcie_rp1 off end |
| 273 | device ref pcie_rp2 off end |
| 274 | device ref pcie_rp3 on end |
| 275 | device ref pcie_rp4 on |
Bora Guvendik | 9d4d2d0 | 2021-03-01 14:32:16 -0800 | [diff] [blame] | 276 | chip soc/intel/common/block/pcie/rtd3 |
| 277 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B17)" |
| 278 | register "srcclk_pin" = "2" |
| 279 | device generic 0 on end |
| 280 | end |
Felix Singer | f13284c | 2024-06-27 21:09:11 +0200 | [diff] [blame] | 281 | end |
| 282 | device ref pcie_rp5 off end |
| 283 | device ref pcie_rp6 off end |
| 284 | device ref pcie_rp7 off end |
| 285 | device ref pcie_rp8 off end |
| 286 | device ref pcie_rp9 on end |
| 287 | device ref pcie_rp10 off end |
| 288 | device ref pcie_rp11 on end |
| 289 | device ref pcie_rp12 off end |
| 290 | device ref uart0 off end |
| 291 | device ref uart1 off end |
| 292 | device ref gspi0 on end |
| 293 | device ref gspi1 on |
Shaunak Saha | b449b9c | 2020-08-23 21:35:21 -0700 | [diff] [blame] | 294 | chip drivers/spi/acpi |
| 295 | register "hid" = "ACPI_DT_NAMESPACE_HID" |
| 296 | register "compat_string" = ""google,cr50"" |
| 297 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C22_IRQ)" |
| 298 | device spi 0 on end |
| 299 | end |
Felix Singer | f13284c | 2024-06-27 21:09:11 +0200 | [diff] [blame] | 300 | end |
| 301 | device ref pch_espi on |
John Zhao | d05b15e | 2020-07-25 17:23:53 -0700 | [diff] [blame] | 302 | chip ec/google/chromeec |
Tim Wawrzynczak | eafe798 | 2020-09-30 13:59:21 -0600 | [diff] [blame] | 303 | use conn0 as mux_conn[0] |
| 304 | use conn1 as mux_conn[1] |
John Zhao | d05b15e | 2020-07-25 17:23:53 -0700 | [diff] [blame] | 305 | device pnp 0c09.0 on end |
| 306 | end |
Felix Singer | f13284c | 2024-06-27 21:09:11 +0200 | [diff] [blame] | 307 | end |
| 308 | device ref p2sb on end |
| 309 | device ref pmc hidden |
John Zhao | 7b46aae | 2020-06-30 15:44:44 -0700 | [diff] [blame] | 310 | # The pmc_mux chip driver is a placeholder for the |
| 311 | # PMC.MUX device in the ACPI hierarchy. |
| 312 | chip drivers/intel/pmc_mux |
| 313 | device generic 0 on |
| 314 | chip drivers/intel/pmc_mux/conn |
Reka Norman | d448f8c | 2021-12-09 12:09:27 +1100 | [diff] [blame] | 315 | use usb2_port6 as usb2_port |
| 316 | use tcss_usb3_port3 as usb3_port |
John Zhao | 7b46aae | 2020-06-30 15:44:44 -0700 | [diff] [blame] | 317 | # SBU is fixed, HSL follows CC |
| 318 | register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" |
Tim Wawrzynczak | eafe798 | 2020-09-30 13:59:21 -0600 | [diff] [blame] | 319 | device generic 0 alias conn0 on end |
John Zhao | 7b46aae | 2020-06-30 15:44:44 -0700 | [diff] [blame] | 320 | end |
| 321 | chip drivers/intel/pmc_mux/conn |
Reka Norman | d448f8c | 2021-12-09 12:09:27 +1100 | [diff] [blame] | 322 | use usb2_port7 as usb2_port |
| 323 | use tcss_usb3_port4 as usb3_port |
John Zhao | 7b46aae | 2020-06-30 15:44:44 -0700 | [diff] [blame] | 324 | # SBU is fixed, HSL follows CC |
| 325 | register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" |
Tim Wawrzynczak | eafe798 | 2020-09-30 13:59:21 -0600 | [diff] [blame] | 326 | device generic 1 alias conn1 on end |
John Zhao | 7b46aae | 2020-06-30 15:44:44 -0700 | [diff] [blame] | 327 | end |
| 328 | end |
| 329 | end |
Felix Singer | f13284c | 2024-06-27 21:09:11 +0200 | [diff] [blame] | 330 | end |
| 331 | device ref hda on end |
| 332 | device ref smbus on end |
| 333 | device ref fast_spi on end |
| 334 | device ref gbe off end |
| 335 | device ref tracehub off end |
Ravi Sarawadi | ebb2d3c | 2019-12-19 23:01:48 -0800 | [diff] [blame] | 336 | end |
| 337 | end |