mb/intel/tglrvp: Update tglrvp_up3 devicetree
Update Tigerlake RVP UP3 devicetree to reflect devices used by
tglrvp_up3.
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Idd0d9efe0ab4e050d2160f7662e4dc40a002672f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37929
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 6a4bae8..fbd1c39 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -4,6 +4,82 @@
device lapic 0 on end
end
+ # FSP configuration
+ register "SaGv" = "SaGv_Disabled"
+ register "SmbusEnable" = "1"
+
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # M.2 Bluetooth
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-C Port4
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB2 Type A port3
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # USB2 Type A port4
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2
+ register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Not used
+ register "usb3_ports[3]" = "USB3_PORT_EMPTY" # USB3/USB2 Flex Connector
+
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+ # EC memory map range is 0x900-0x9ff
+ register "gen3_dec" = "0x00fc0901"
+
+ register "PrmrrSize" = "0x10000000"
+
+ register "PcieRpEnable[2]" = "1"
+ register "PcieRpEnable[3]" = "1"
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpEnable[9]" = "1"
+
+ register "PcieClkSrcClkReq[1]" = "1"
+ register "PcieClkSrcClkReq[2]" = "2"
+ register "PcieClkSrcClkReq[3]" = "3"
+
+ register "PcieClkSrcUsage[1]" = "0x2"
+ register "PcieClkSrcUsage[2]" = "0x3"
+ register "PcieClkSrcUsage[3]" = "0x8"
+
+ register "SerialIoI2cMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoPci,
+ [PchSerialIoIndexI2C3] = PchSerialIoPci,
+ [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C5] = PchSerialIoPci,
+ }"
+
+ register "SerialIoGSpiMode" = "{
+ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+ [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+ [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
+ [PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
+ }"
+
+ register "SerialIoGSpiCsMode" = "{
+ [PchSerialIoIndexGSPI0] = 0,
+ [PchSerialIoIndexGSPI1] = 0,
+ [PchSerialIoIndexGSPI2] = 0,
+ [PchSerialIoIndexGSPI3] = 0,
+ }"
+
+ register "SerialIoGSpiCsState" = "{
+ [PchSerialIoIndexGSPI0] = 0,
+ [PchSerialIoIndexGSPI1] = 0,
+ [PchSerialIoIndexGSPI2] = 0,
+ [PchSerialIoIndexGSPI3] = 0,
+ }"
+
+ register "SerialIoUartMode" = "{
+ [PchSerialIoIndexUART0] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART2] = PchSerialIoPci,
+ }"
device domain 0 on
#From EDS(575683)