| commit | 23d3ad0f640c32a452cc36eb3040f324feeee3e8 | [log] [tgz] |
|---|---|---|
| author | John Zhao <john.zhao@intel.com> | Tue Jun 30 17:36:24 2020 -0700 |
| committer | Patrick Georgi <pgeorgi@google.com> | Sun Jul 12 19:31:01 2020 +0000 |
| tree | 67d48f7afd89e9af8067d06b26e7465ec3d671bf | |
| parent | ef079c86ea3c24dd30d1bbad2e446632ec1c0104 [diff] [blame] |
mb/intel/tglrvp: Enable s0ix for tglrvp up3 and up4 This change enables s0ix for tglrvp up3 and up4 platform. TEST=Built image and booted to kernel. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I657bee1d7ee120ae15ccb4a33f9eb2fcf5cca65a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42954 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 612a97d..b4a121a95 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -114,6 +114,9 @@ register "TcssXhciEn" = "1" register "TcssAuxOri" = "0" + # Enable S0ix + register "s0ix_enable" = "1" + # D3Hot and D3Cold for TCSS register "TcssD3HotEnable" = "1" register "TcssD3ColdEnable" = "1"