Ravi Sarawadi | ebb2d3c | 2019-12-19 23:01:48 -0800 | [diff] [blame] | 1 | chip soc/intel/tigerlake |
| 2 | |
| 3 | device cpu_cluster 0 on |
| 4 | device lapic 0 on end |
| 5 | end |
| 6 | |
Shaunak Saha | d72cca0 | 2020-03-25 11:42:12 -0700 | [diff] [blame] | 7 | # GPE configuration |
| 8 | # Note that GPE events called out in ASL code rely on this |
| 9 | # route. i.e. If this route changes then the affected GPE |
| 10 | # offset bits also need to be changed. |
| 11 | register "pmc_gpe0_dw0" = "GPP_B" |
| 12 | register "pmc_gpe0_dw1" = "GPP_D" |
| 13 | register "pmc_gpe0_dw2" = "GPP_E" |
| 14 | |
Ravi Sarawadi | 97e1e3e | 2019-12-24 15:54:56 -0800 | [diff] [blame] | 15 | # FSP configuration |
| 16 | register "SaGv" = "SaGv_Disabled" |
| 17 | register "SmbusEnable" = "1" |
| 18 | |
| 19 | register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 |
| 20 | register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN |
| 21 | register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # M.2 Bluetooth |
| 22 | register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 |
| 23 | register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 |
| 24 | register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 |
| 25 | register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-C Port4 |
| 26 | register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 |
| 27 | register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB2 Type A port3 |
| 28 | register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # USB2 Type A port4 |
| 29 | |
| 30 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 |
| 31 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 |
| 32 | register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Not used |
| 33 | register "usb3_ports[3]" = "USB3_PORT_EMPTY" # USB3/USB2 Flex Connector |
| 34 | |
Jamie Ryu | ef079c8 | 2020-06-24 15:55:10 -0700 | [diff] [blame] | 35 | # CPU replacement check |
| 36 | register "CpuReplacementCheck" = "1" |
| 37 | |
Ravi Sarawadi | 97e1e3e | 2019-12-24 15:54:56 -0800 | [diff] [blame] | 38 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 39 | register "gen1_dec" = "0x00fc0801" |
| 40 | register "gen2_dec" = "0x000c0201" |
| 41 | # EC memory map range is 0x900-0x9ff |
| 42 | register "gen3_dec" = "0x00fc0901" |
| 43 | |
Ravi Sarawadi | 97e1e3e | 2019-12-24 15:54:56 -0800 | [diff] [blame] | 44 | register "PcieRpEnable[2]" = "1" |
| 45 | register "PcieRpEnable[3]" = "1" |
| 46 | register "PcieRpEnable[8]" = "1" |
Wonkyu Kim | 06e067e | 2020-01-22 23:48:52 -0800 | [diff] [blame] | 47 | register "PcieRpEnable[10]" = "1" |
Ravi Sarawadi | 97e1e3e | 2019-12-24 15:54:56 -0800 | [diff] [blame] | 48 | |
Wonkyu Kim | 53ac68e | 2020-04-07 23:37:11 -0700 | [diff] [blame] | 49 | # Enable RP LTR |
| 50 | register "PcieRpLtrEnable[2]" = "1" |
| 51 | register "PcieRpLtrEnable[3]" = "1" |
| 52 | register "PcieRpLtrEnable[8]" = "1" |
| 53 | register "PcieRpLtrEnable[10]" = "1" |
| 54 | |
Wonkyu Kim | f787e87 | 2020-03-03 01:58:17 -0800 | [diff] [blame] | 55 | # Hybrid storage mode |
| 56 | register "HybridStorageMode" = "1" |
| 57 | |
Ravi Sarawadi | 97e1e3e | 2019-12-24 15:54:56 -0800 | [diff] [blame] | 58 | register "PcieClkSrcClkReq[1]" = "1" |
| 59 | register "PcieClkSrcClkReq[2]" = "2" |
| 60 | register "PcieClkSrcClkReq[3]" = "3" |
| 61 | |
| 62 | register "PcieClkSrcUsage[1]" = "0x2" |
| 63 | register "PcieClkSrcUsage[2]" = "0x3" |
| 64 | register "PcieClkSrcUsage[3]" = "0x8" |
| 65 | |
Wonkyu Kim | d250063 | 2020-01-21 21:54:14 -0800 | [diff] [blame] | 66 | register "SataSalpSupport" = "1" |
| 67 | register "SataPortsEnable[0]" = "1" |
| 68 | register "SataPortsEnable[1]" = "1" |
| 69 | |
Wonkyu Kim | 46cef44 | 2020-01-23 00:12:46 -0800 | [diff] [blame] | 70 | # enabling EDP in PortA |
| 71 | register "DdiPortAConfig" = "1" |
| 72 | |
Wonkyu Kim | 34944be | 2020-03-02 22:18:26 -0800 | [diff] [blame] | 73 | register "DdiPortBHpd" = "1" |
Wonkyu Kim | 46cef44 | 2020-01-23 00:12:46 -0800 | [diff] [blame] | 74 | register "DdiPort1Hpd" = "1" |
| 75 | register "DdiPort1Ddc" = "1" |
| 76 | |
Ravi Sarawadi | 97e1e3e | 2019-12-24 15:54:56 -0800 | [diff] [blame] | 77 | register "SerialIoI2cMode" = "{ |
| 78 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 79 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 80 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
| 81 | [PchSerialIoIndexI2C3] = PchSerialIoPci, |
| 82 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| 83 | [PchSerialIoIndexI2C5] = PchSerialIoPci, |
| 84 | }" |
| 85 | |
| 86 | register "SerialIoGSpiMode" = "{ |
| 87 | [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, |
| 88 | [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, |
| 89 | [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, |
| 90 | [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, |
| 91 | }" |
| 92 | |
| 93 | register "SerialIoGSpiCsMode" = "{ |
| 94 | [PchSerialIoIndexGSPI0] = 0, |
| 95 | [PchSerialIoIndexGSPI1] = 0, |
| 96 | [PchSerialIoIndexGSPI2] = 0, |
| 97 | [PchSerialIoIndexGSPI3] = 0, |
| 98 | }" |
| 99 | |
| 100 | register "SerialIoGSpiCsState" = "{ |
| 101 | [PchSerialIoIndexGSPI0] = 0, |
| 102 | [PchSerialIoIndexGSPI1] = 0, |
| 103 | [PchSerialIoIndexGSPI2] = 0, |
| 104 | [PchSerialIoIndexGSPI3] = 0, |
| 105 | }" |
| 106 | |
| 107 | register "SerialIoUartMode" = "{ |
| 108 | [PchSerialIoIndexUART0] = PchSerialIoDisabled, |
| 109 | [PchSerialIoIndexUART1] = PchSerialIoDisabled, |
| 110 | [PchSerialIoIndexUART2] = PchSerialIoPci, |
| 111 | }" |
Ravi Sarawadi | ebb2d3c | 2019-12-19 23:01:48 -0800 | [diff] [blame] | 112 | |
John Zhao | b1c53fc | 2020-05-13 16:27:03 -0700 | [diff] [blame] | 113 | # TCSS USB3 |
| 114 | register "TcssXhciEn" = "1" |
| 115 | register "TcssAuxOri" = "0" |
| 116 | |
John Zhao | 23d3ad0 | 2020-06-30 17:36:24 -0700 | [diff] [blame] | 117 | # Enable S0ix |
| 118 | register "s0ix_enable" = "1" |
| 119 | |
John Zhao | 3c8cb24 | 2020-05-19 20:21:00 -0700 | [diff] [blame] | 120 | # D3Hot and D3Cold for TCSS |
| 121 | register "TcssD3HotEnable" = "1" |
| 122 | register "TcssD3ColdEnable" = "1" |
| 123 | |
Srinidhi N Kaushik | b2ecc57 | 2020-01-24 10:43:48 -0800 | [diff] [blame] | 124 | #HD Audio |
| 125 | register "PchHdaDspEnable" = "1" |
| 126 | register "PchHdaAudioLinkHdaEnable" = "0" |
| 127 | register "PchHdaAudioLinkDmicEnable[0]" = "1" |
| 128 | register "PchHdaAudioLinkDmicEnable[1]" = "1" |
| 129 | register "PchHdaAudioLinkSspEnable[0]" = "1" |
Srinidhi N Kaushik | 6975e07 | 2020-03-12 01:22:01 -0700 | [diff] [blame] | 130 | register "PchHdaAudioLinkSspEnable[1]" = "0" |
| 131 | register "PchHdaAudioLinkSspEnable[2]" = "1" |
| 132 | register "PchHdaAudioLinkSndwEnable[0]" = "1" |
Srinidhi N Kaushik | b2ecc57 | 2020-01-24 10:43:48 -0800 | [diff] [blame] | 133 | |
Wonkyu Kim | 5c27182 | 2020-04-03 00:42:22 -0700 | [diff] [blame] | 134 | # Intel Common SoC Config |
| 135 | register "common_soc_config" = "{ |
| 136 | .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
| 137 | .i2c[0] = { |
| 138 | .speed = I2C_SPEED_FAST, |
| 139 | }, |
| 140 | .i2c[1] = { |
| 141 | .speed = I2C_SPEED_FAST, |
| 142 | }, |
| 143 | .i2c[2] = { |
| 144 | .speed = I2C_SPEED_FAST, |
| 145 | }, |
| 146 | .i2c[3] = { |
| 147 | .speed = I2C_SPEED_FAST, |
| 148 | }, |
| 149 | .i2c[5] = { |
| 150 | .speed = I2C_SPEED_FAST, |
| 151 | }, |
| 152 | }" |
| 153 | |
Ravi Sarawadi | ebb2d3c | 2019-12-19 23:01:48 -0800 | [diff] [blame] | 154 | device domain 0 on |
| 155 | #From EDS(575683) |
| 156 | device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y |
| 157 | device pci 02.0 on end # Graphics |
| 158 | device pci 04.0 on end # DPTF 0x9A03 |
| 159 | device pci 05.0 on end # IPU 0x9A19 |
| 160 | device pci 06.0 on end # PEG60 0x9A09 |
John Zhao | b1c53fc | 2020-05-13 16:27:03 -0700 | [diff] [blame] | 161 | device pci 07.0 on end # TBT_PCIe0 0x9A23 |
| 162 | device pci 07.1 on end # TBT_PCIe1 0x9A25 |
| 163 | device pci 07.2 on end # TBT_PCIe2 0x9A27 |
| 164 | device pci 07.3 on end # TBT_PCIe3 0x9A29 |
Ravi Sarawadi | ebb2d3c | 2019-12-19 23:01:48 -0800 | [diff] [blame] | 165 | device pci 08.0 off end # GNA 0x9A11 |
| 166 | device pci 09.0 off end # NPK 0x9A33 |
| 167 | device pci 0a.0 off end # Crash-log SRAM 0x9A0D |
| 168 | device pci 0d.0 on end # USB xHCI 0x9A13 |
| 169 | device pci 0d.1 on end # USB xDCI (OTG) 0x9A15 |
John Zhao | b1c53fc | 2020-05-13 16:27:03 -0700 | [diff] [blame] | 170 | device pci 0d.2 on end # TBT DMA0 0x9A1B |
| 171 | device pci 0d.3 on end # TBT DMA1 0x9A1D |
Wonkyu Kim | 165efa1 | 2020-05-05 09:10:13 -0700 | [diff] [blame] | 172 | device pci 0e.0 off end # VMD 0x9A0B |
Ravi Sarawadi | ebb2d3c | 2019-12-19 23:01:48 -0800 | [diff] [blame] | 173 | |
| 174 | # From PCH EDS(576591) |
Srinidhi N Kaushik | 3663d55 | 2020-03-12 01:08:14 -0700 | [diff] [blame] | 175 | device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7 |
Ravi Sarawadi | ebb2d3c | 2019-12-19 23:01:48 -0800 | [diff] [blame] | 176 | device pci 10.6 off end # THC0 0xA0D0 |
| 177 | device pci 10.7 off end # THC1 0xA0D1 |
li feng | 2395425 | 2020-03-12 16:38:34 -0700 | [diff] [blame] | 178 | device pci 12.0 on # SensorHUB 0xA0FC |
| 179 | chip drivers/intel/ish |
| 180 | register "firmware_name" = ""tglrvp_ish.bin"" |
| 181 | device generic 0 on end |
| 182 | end |
| 183 | end |
Ravi Sarawadi | ebb2d3c | 2019-12-19 23:01:48 -0800 | [diff] [blame] | 184 | device pci 12.6 off end # GSPI2 0x34FB |
| 185 | device pci 13.0 off end # GSPI3 0xA0FD |
Elyes HAOUAS | fd8de18 | 2020-03-31 21:42:02 +0200 | [diff] [blame] | 186 | device pci 14.0 on end # USB3.1 xHCI 0xA0ED |
Ravi Sarawadi | ebb2d3c | 2019-12-19 23:01:48 -0800 | [diff] [blame] | 187 | device pci 14.1 on end # USB3.1 xDCI 0xA0EE |
| 188 | device pci 14.2 on end # Shared RAM 0xA0EF |
Srinidhi N Kaushik | dcd3d07 | 2020-03-05 00:41:14 -0800 | [diff] [blame] | 189 | chip drivers/intel/wifi |
| 190 | register "wake" = "GPE0_PME_B0" |
| 191 | device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 |
| 192 | end |
| 193 | |
Elyes HAOUAS | fd8de18 | 2020-03-31 21:42:02 +0200 | [diff] [blame] | 194 | device pci 15.0 on # I2C0 0xA0E8 |
Shaunak Saha | 48b388f | 2020-05-27 22:48:57 -0700 | [diff] [blame] | 195 | chip drivers/i2c/generic |
| 196 | register "hid" = ""10EC1308"" |
| 197 | register "name" = ""RTAM"" |
| 198 | register "desc" = ""Realtek RT1308 Codec"" |
| 199 | device i2c 10 on end |
| 200 | end |
Srinidhi N Kaushik | b2ecc57 | 2020-01-24 10:43:48 -0800 | [diff] [blame] | 201 | chip drivers/i2c/max98373 |
| 202 | register "vmon_slot_no" = "4" |
| 203 | register "imon_slot_no" = "5" |
| 204 | register "uid" = "0" |
| 205 | register "desc" = ""RIGHT SPEAKER AMP"" |
| 206 | register "name" = ""MAXR"" |
| 207 | device i2c 31 on end |
| 208 | end |
| 209 | chip drivers/i2c/max98373 |
| 210 | register "vmon_slot_no" = "6" |
| 211 | register "imon_slot_no" = "7" |
| 212 | register "uid" = "1" |
| 213 | register "desc" = ""LEFT SPEAKER AMP"" |
| 214 | register "name" = ""MAXL"" |
| 215 | device i2c 32 on end |
| 216 | end |
| 217 | chip drivers/i2c/generic |
| 218 | register "hid" = ""10EC5682"" |
| 219 | register "name" = ""RT58"" |
| 220 | register "desc" = ""Realtek RT5682"" |
| 221 | register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_C12_IRQ)" |
| 222 | register "probed" = "1" |
| 223 | # Set the jd_src to RT5668_JD1 for jack detection |
| 224 | register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" |
| 225 | register "property_list[0].name" = ""realtek,jd-src"" |
| 226 | register "property_list[0].integer" = "1" |
| 227 | device i2c 1a on end |
| 228 | end |
| 229 | end # I2C0 |
Ravi Sarawadi | ebb2d3c | 2019-12-19 23:01:48 -0800 | [diff] [blame] | 230 | device pci 15.1 on end # I2C1 0xA0E9 |
| 231 | device pci 15.2 on end # I2C2 0xA0EA |
| 232 | device pci 15.3 on end # I2C3 0xA0EB |
| 233 | device pci 16.0 on end # HECI1 0xA0E0 |
| 234 | device pci 16.1 off end # HECI2 0xA0E1 |
| 235 | device pci 16.2 off end # CSME 0xA0E2 |
| 236 | device pci 16.3 off end # CSME 0xA0E3 |
| 237 | device pci 16.4 off end # HECI3 0xA0E4 |
| 238 | device pci 16.5 off end # HECI4 0xA0E5 |
Wonkyu Kim | d250063 | 2020-01-21 21:54:14 -0800 | [diff] [blame] | 239 | device pci 17.0 on end # SATA 0xA0D3 |
Ravi Sarawadi | ebb2d3c | 2019-12-19 23:01:48 -0800 | [diff] [blame] | 240 | device pci 19.0 off end # I2C4 0xA0C5 |
| 241 | device pci 19.1 on end # I2C5 0xA0C6 |
| 242 | device pci 19.2 on end # UART2 0xA0C7 |
| 243 | device pci 1c.0 off end # RP1 0xA0B8 |
| 244 | device pci 1c.1 off end # RP2 0xA0B9 |
| 245 | device pci 1c.2 on end # RP3 0xA0BA |
| 246 | device pci 1c.3 on end # RP4 0xA0BB |
| 247 | device pci 1c.4 off end # RP5 0xA0BC |
| 248 | device pci 1c.5 off end # RP6 0xA0BD |
| 249 | device pci 1c.6 off end # RP7 0xA0BE |
| 250 | device pci 1c.7 off end # RP8 0xA0BF |
| 251 | device pci 1d.0 on end # RP9 0xA0B0 |
Wonkyu Kim | 06e067e | 2020-01-22 23:48:52 -0800 | [diff] [blame] | 252 | device pci 1d.1 off end # RP10 0xA0B1 |
| 253 | device pci 1d.2 on end # RP11 0xA0B2 |
Ravi Sarawadi | ebb2d3c | 2019-12-19 23:01:48 -0800 | [diff] [blame] | 254 | device pci 1d.3 off end # RP12 0xA0B3 |
| 255 | device pci 1e.0 off end # UART0 0xA0A8 |
| 256 | device pci 1e.1 off end # UART1 0xA0A9 |
| 257 | device pci 1e.2 off end # GSPI0 0xA0AA |
| 258 | device pci 1e.3 off end # GSPI1 0xA0AB |
John Zhao | d05b15e | 2020-07-25 17:23:53 -0700 | [diff] [blame^] | 259 | device pci 1f.0 on |
| 260 | chip ec/google/chromeec |
| 261 | device pnp 0c09.0 on end |
| 262 | end |
| 263 | end # eSPI 0xA080 - A09F |
Ravi Sarawadi | ebb2d3c | 2019-12-19 23:01:48 -0800 | [diff] [blame] | 264 | device pci 1f.1 on end # P2SB 0xA0A0 |
John Zhao | 7b46aae | 2020-06-30 15:44:44 -0700 | [diff] [blame] | 265 | device pci 1f.2 hidden # PMC 0xA0A1 |
| 266 | # The pmc_mux chip driver is a placeholder for the |
| 267 | # PMC.MUX device in the ACPI hierarchy. |
| 268 | chip drivers/intel/pmc_mux |
| 269 | device generic 0 on |
| 270 | chip drivers/intel/pmc_mux/conn |
| 271 | register "usb2_port_number" = "6" |
| 272 | register "usb3_port_number" = "3" |
| 273 | # SBU is fixed, HSL follows CC |
| 274 | register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" |
| 275 | device generic 0 on end |
| 276 | end |
| 277 | chip drivers/intel/pmc_mux/conn |
| 278 | register "usb2_port_number" = "7" |
| 279 | register "usb3_port_number" = "4" |
| 280 | # SBU is fixed, HSL follows CC |
| 281 | register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" |
| 282 | device generic 1 on end |
| 283 | end |
| 284 | end |
| 285 | end |
| 286 | end # PMC |
Ravi Sarawadi | ebb2d3c | 2019-12-19 23:01:48 -0800 | [diff] [blame] | 287 | device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF |
| 288 | device pci 1f.4 on end # SMBus 0xA0A3 |
| 289 | device pci 1f.5 on end # SPI 0xA0A4 |
| 290 | device pci 1f.6 off end # GbE 0x15E1/0x15E2 |
| 291 | device pci 1f.7 off end # TH 0xA0A6 |
| 292 | end |
| 293 | end |