mb/intel/tglrvp: Add support for USB Type-C connector device properties
This change updates TGLRVP configuration to have USB Type-C connector
device properties filled into ACPI SSDT.
TEST=Built and booted to kernel on tglrvp boards. Verified the USBC
scope under LPCB.EC0.CREC with required connector device properties.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ifd4c59afb3b8a222598fd4ff36d72c4b877bdad2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index b4a121a95..e8dc7bd 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -256,7 +256,11 @@
device pci 1e.1 off end # UART1 0xA0A9
device pci 1e.2 off end # GSPI0 0xA0AA
device pci 1e.3 off end # GSPI1 0xA0AB
- device pci 1f.0 on end # eSPI 0xA080 - A09F
+ device pci 1f.0 on
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end # eSPI 0xA080 - A09F
device pci 1f.1 on end # P2SB 0xA0A0
device pci 1f.2 hidden # PMC 0xA0A1
# The pmc_mux chip driver is a placeholder for the