mb, soc/intel: Reorganize CNVi device entries in devicetree
This change reorganizes the CNVi device entries in mainboard
devicetree/overridetree and SoC chipset tree to make it consistent
with how other SoC internal PCI devices are represented i.e. without a
chip driver around the SoC controller itself.
Before:
chip drivers/wifi/generic
register "wake" = "..."
device pci xx.y on end
end
After:
device pci xx.y on
chip drivers/wifi/generic
register "wake" = "..."
device generic 0 on end
end
end
Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index e16bd1f..57f36ab 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -227,10 +227,12 @@
device pci 14.0 on end # USB3.1 xHCI 0xA0ED
device pci 14.1 on end # USB3.1 xDCI 0xA0EE
device pci 14.2 on end # Shared RAM 0xA0EF
- chip drivers/wifi/generic
- register "wake" = "GPE0_PME_B0"
- device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3
- end
+ device pci 14.3 on
+ chip drivers/wifi/generic
+ register "wake" = "GPE0_PME_B0"
+ device generic 0 on end
+ end
+ end # CNVi: WiFi 0xA0F0 - A0F3
device pci 15.0 on # I2C0 0xA0E8
chip drivers/i2c/generic