| commit | c7fe0bd8d6aee67b746f2d5168b7fcd4b85a0e3d | [log] [tgz] |
|---|---|---|
| author | Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> | Tue Jul 07 18:25:45 2020 -0700 |
| committer | Duncan Laurie <dlaurie@chromium.org> | Mon Aug 10 15:24:27 2020 +0000 |
| tree | daabba4c98ae29e45007866b93091dbd810ab782 | |
| parent | a815272b7b9dbf23ac170ec6c7ec44093cd52406 [diff] [blame] |
mb/tgl: Enable SaGv for TGL-UP3 RVP BUG=none BRANCH=none TEST=Build and boot TGL-UP3 RVP with QS silicon successfully. Change-Id: I5b84457a1455edfe500ce80ba7f7ca6ccce43666 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43276 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 5d4d246..2dd65c4 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -13,7 +13,7 @@ register "pmc_gpe0_dw2" = "GPP_E" # FSP configuration - register "SaGv" = "SaGv_Disabled" + register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1