mb/tglrvp: Add GPE configuration
Update the GPE configuration for dw0, dw1 and dw2.
BUG=None
TEST=build and boot tglrvp
Change-Id: I8b406bcbd710e84cec91a8c2d1557902e929f7cc
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39844
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 23737c3..8fd9087 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -4,6 +4,14 @@
device lapic 0 on end
end
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "pmc_gpe0_dw0" = "GPP_B"
+ register "pmc_gpe0_dw1" = "GPP_D"
+ register "pmc_gpe0_dw2" = "GPP_E"
+
# FSP configuration
register "SaGv" = "SaGv_Disabled"
register "SmbusEnable" = "1"