Arthur Heymans | 4c7979a | 2019-06-17 14:30:10 +0200 | [diff] [blame] | 1 | config SOC_INTEL_COMMON_SKYLAKE_BASE |
2 | bool | ||||
3 | |||||
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 4 | config SOC_INTEL_SKYLAKE |
5 | bool | ||||
Arthur Heymans | 4c7979a | 2019-06-17 14:30:10 +0200 | [diff] [blame] | 6 | select SOC_INTEL_COMMON_SKYLAKE_BASE |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 7 | help |
8 | Intel Skylake support | ||||
9 | |||||
Rizwan Qureshi | 0700dca | 2017-02-09 15:57:45 +0530 | [diff] [blame] | 10 | config SOC_INTEL_KABYLAKE |
11 | bool | ||||
Arthur Heymans | 4c7979a | 2019-06-17 14:30:10 +0200 | [diff] [blame] | 12 | select SOC_INTEL_COMMON_SKYLAKE_BASE |
Rizwan Qureshi | 0700dca | 2017-02-09 15:57:45 +0530 | [diff] [blame] | 13 | help |
14 | Intel Kabylake support | ||||
15 | |||||
Arthur Heymans | 4c7979a | 2019-06-17 14:30:10 +0200 | [diff] [blame] | 16 | if SOC_INTEL_COMMON_SKYLAKE_BASE |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 17 | |
18 | config CPU_SPECIFIC_OPTIONS | ||||
19 | def_bool y | ||||
Aaron Durbin | e0a4914 | 2016-07-13 23:20:51 -0500 | [diff] [blame] | 20 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Vadim Bendebury | 5542bb6 | 2018-02-05 19:59:09 -0800 | [diff] [blame] | 21 | select ACPI_NHLT |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 22 | select ARCH_BOOTBLOCK_X86_32 |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 23 | select ARCH_RAMSTAGE_X86_32 |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 24 | select ARCH_ROMSTAGE_X86_32 |
25 | select ARCH_VERSTAGE_X86_32 | ||||
Aaron Durbin | e4cc8cd | 2016-08-11 23:55:39 -0500 | [diff] [blame] | 26 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
Aaron Durbin | e8e118d | 2016-08-12 15:00:10 -0500 | [diff] [blame] | 27 | select BOOT_DEVICE_SUPPORTS_WRITES |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 28 | select CACHE_MRC_SETTINGS |
Nico Huber | 6275e34 | 2018-11-21 00:11:35 +0100 | [diff] [blame] | 29 | select CPU_INTEL_COMMON |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 30 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Michael Niewöhner | 7bdedcd | 2019-09-01 16:49:09 +0200 | [diff] [blame] | 31 | select CPU_INTEL_COMMON_HYPERTHREADING |
Michael Niewöhner | 0f91f79 | 2019-10-05 19:47:47 +0200 | [diff] [blame] | 32 | select FSP_M_XIP |
Aaron Durbin | ffdf901 | 2015-07-24 13:00:36 -0500 | [diff] [blame] | 33 | select GENERIC_GPIO_LIB |
Vadim Bendebury | 5542bb6 | 2018-02-05 19:59:09 -0800 | [diff] [blame] | 34 | select HAVE_FSP_GOP |
Wim Vervoorn | d137150 | 2019-12-17 14:10:16 +0100 | [diff] [blame] | 35 | select HAVE_FSP_LOGO_SUPPORT |
Stefan Tauner | ef8b957 | 2018-09-06 00:34:28 +0200 | [diff] [blame] | 36 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 37 | select HAVE_SMI_HANDLER |
Patrick Rudolph | c7edf18 | 2017-09-26 19:34:35 +0200 | [diff] [blame] | 38 | select INTEL_GMA_ACPI |
Michael Niewöhner | 0f91f79 | 2019-10-05 19:47:47 +0200 | [diff] [blame] | 39 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
Johanna Schander | 8a6e036 | 2019-12-08 15:54:09 +0100 | [diff] [blame] | 40 | select HAVE_INTEL_FSP_REPO |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 41 | select IOAPIC |
Duncan Laurie | 205ed2d | 2016-06-02 15:23:42 -0700 | [diff] [blame] | 42 | select MRC_SETTINGS_PROTECT |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 43 | select PARALLEL_MP |
Furquan Shaikh | a585358 | 2017-05-06 12:40:15 -0700 | [diff] [blame] | 44 | select PARALLEL_MP_AP_WORK |
Michael Niewöhner | 0f91f79 | 2019-10-05 19:47:47 +0200 | [diff] [blame] | 45 | select PLATFORM_USES_FSP2_0 |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 46 | select REG_SCRIPT |
Subrata Banik | 46a7178 | 2017-06-02 18:52:24 +0530 | [diff] [blame] | 47 | select SA_ENABLE_DPR |
Julien Viard de Galbert | 2912e8e | 2018-08-14 16:15:26 +0200 | [diff] [blame] | 48 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 49 | select SOC_INTEL_COMMON |
Duncan Laurie | a1c8b34d | 2015-09-08 16:12:44 -0700 | [diff] [blame] | 50 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Subrata Banik | e074d62 | 2017-02-16 16:16:37 +0530 | [diff] [blame] | 51 | select SOC_INTEL_COMMON_BLOCK |
Nico Huber | 2f1ef98 | 2018-11-07 16:24:50 +0100 | [diff] [blame] | 52 | select SOC_INTEL_COMMON_BLOCK_CAR |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 53 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Barnali Sarkar | 0a203d1 | 2017-05-04 18:02:17 +0530 | [diff] [blame] | 54 | select SOC_INTEL_COMMON_BLOCK_CPU |
Barnali Sarkar | 7327386 | 2017-06-13 20:22:33 +0530 | [diff] [blame] | 55 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
Furquan Shaikh | 2c36889 | 2018-10-18 16:22:37 -0700 | [diff] [blame] | 56 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
Hannah Williams | 1760cd3 | 2017-04-06 20:54:11 -0700 | [diff] [blame] | 57 | select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS |
Vadim Bendebury | 5542bb6 | 2018-02-05 19:59:09 -0800 | [diff] [blame] | 58 | select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL |
Furquan Shaikh | 05a6f29 | 2017-03-31 14:02:47 -0700 | [diff] [blame] | 59 | select SOC_INTEL_COMMON_BLOCK_GSPI |
Furquan Shaikh | 31bff01 | 2018-09-29 23:31:04 -0700 | [diff] [blame] | 60 | select SOC_INTEL_COMMON_BLOCK_HDA |
Subrata Banik | 93ebe49 | 2017-03-14 18:24:47 +0530 | [diff] [blame] | 61 | select SOC_INTEL_COMMON_BLOCK_SA |
Duncan Laurie | 1e06611 | 2020-04-08 11:35:52 -0700 | [diff] [blame] | 62 | select SOC_INTEL_COMMON_BLOCK_SCS |
Pratik Prajapati | a04aa3d | 2017-06-12 23:02:36 -0700 | [diff] [blame] | 63 | select SOC_INTEL_COMMON_BLOCK_SGX |
Michael Niewöhner | c169a47 | 2019-10-31 19:01:23 +0100 | [diff] [blame] | 64 | select SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY |
Subrata Banik | ece173c | 2017-12-14 18:18:34 +0530 | [diff] [blame] | 65 | select SOC_INTEL_COMMON_BLOCK_SMM |
66 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP | ||||
Subrata Banik | 2fff391 | 2020-01-16 10:13:28 +0530 | [diff] [blame] | 67 | select SOC_INTEL_COMMON_BLOCK_THERMAL |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 68 | select SOC_INTEL_COMMON_BLOCK_UART |
Karthikeyan Ramasubramanian | cc7cdb1 | 2019-03-20 11:38:01 -0600 | [diff] [blame] | 69 | select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG |
Subrata Banik | f513ceb | 2018-05-17 15:57:43 +0530 | [diff] [blame] | 70 | select SOC_INTEL_COMMON_PCH_BASE |
Aaron Durbin | c14a1a9 | 2016-06-28 15:41:07 -0500 | [diff] [blame] | 71 | select SOC_INTEL_COMMON_NHLT |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 72 | select SOC_INTEL_COMMON_RESET |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 73 | select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT |
Nico Huber | dd274e2 | 2020-04-26 20:37:32 +0200 | [diff] [blame] | 74 | select SOC_INTEL_CONFIGURE_DDI_A_4_LANES |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 75 | select SSE2 |
76 | select SUPPORT_CPU_UCODE_IN_CBFS | ||||
Aamir Bohra | 842776e | 2017-05-25 14:12:01 +0530 | [diff] [blame] | 77 | select TSC_MONOTONIC_TIMER |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 78 | select TSC_SYNC_MFENCE |
79 | select UDELAY_TSC | ||||
Michael Niewöhner | 0f91f79 | 2019-10-05 19:47:47 +0200 | [diff] [blame] | 80 | select UDK_2015_BINDING |
Aamir Bohra | c1d227d | 2020-07-16 09:03:06 +0530 | [diff] [blame^] | 81 | select USE_CAR_NEM_ENHANCED_V1 |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 82 | |
Patrick Rudolph | 203061c | 2019-09-02 09:35:21 +0200 | [diff] [blame] | 83 | config FSP_HYPERTHREADING |
84 | bool "Enable Hyper-Threading" | ||||
Patrick Rudolph | 203061c | 2019-09-02 09:35:21 +0200 | [diff] [blame] | 85 | default y |
86 | |||||
Arthur Heymans | 27d3f71 | 2018-01-05 17:51:46 +0100 | [diff] [blame] | 87 | config CPU_INTEL_NUM_FIT_ENTRIES |
88 | int | ||||
89 | default 10 | ||||
90 | |||||
Furquan Shaikh | 610a33a | 2016-07-22 16:17:53 -0700 | [diff] [blame] | 91 | config CHROMEOS |
92 | select CHROMEOS_RAMOOPS_DYNAMIC | ||||
Julius Werner | 58c3938 | 2017-02-13 17:53:29 -0800 | [diff] [blame] | 93 | |
94 | config VBOOT | ||||
Julius Werner | 58c3938 | 2017-02-13 17:53:29 -0800 | [diff] [blame] | 95 | select VBOOT_SEPARATE_VERSTAGE |
Joel Kitching | 6672bd8 | 2019-04-10 16:06:21 +0800 | [diff] [blame] | 96 | select VBOOT_MUST_REQUEST_DISPLAY |
Aaron Durbin | a6914d2 | 2016-08-24 08:49:29 -0500 | [diff] [blame] | 97 | select VBOOT_STARTS_IN_BOOTBLOCK |
Furquan Shaikh | 2a12e2e | 2016-07-25 11:48:03 -0700 | [diff] [blame] | 98 | select VBOOT_VBNV_CMOS |
99 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH | ||||
Furquan Shaikh | 610a33a | 2016-07-22 16:17:53 -0700 | [diff] [blame] | 100 | |
Martin Roth | 59ff340 | 2016-02-09 09:06:46 -0700 | [diff] [blame] | 101 | config CBFS_SIZE |
102 | hex | ||||
103 | default 0x200000 | ||||
104 | |||||
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 105 | config DCACHE_RAM_BASE |
Arthur Heymans | 432ac61 | 2017-06-13 14:17:05 +0200 | [diff] [blame] | 106 | hex |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 107 | default 0xfef00000 |
108 | |||||
109 | config DCACHE_RAM_SIZE | ||||
Arthur Heymans | 432ac61 | 2017-06-13 14:17:05 +0200 | [diff] [blame] | 110 | hex |
Rizwan Qureshi | 3ad6356 | 2016-08-14 15:48:33 +0530 | [diff] [blame] | 111 | default 0x40000 |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 112 | help |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 113 | The size of the cache-as-ram region required during bootblock |
114 | and/or romstage. | ||||
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 115 | |
Subrata Banik | 68d5d8b | 2016-07-18 14:13:52 +0530 | [diff] [blame] | 116 | config DCACHE_BSP_STACK_SIZE |
117 | hex | ||||
118 | default 0x4000 | ||||
119 | help | ||||
120 | The amount of anticipated stack usage in CAR by bootblock and | ||||
121 | other stages. | ||||
122 | |||||
123 | config C_ENV_BOOTBLOCK_SIZE | ||||
124 | hex | ||||
Furquan Shaikh | 7038596 | 2016-08-24 10:28:30 -0700 | [diff] [blame] | 125 | default 0xC000 |
Subrata Banik | 68d5d8b | 2016-07-18 14:13:52 +0530 | [diff] [blame] | 126 | |
Subrata Banik | 086730b | 2015-12-02 11:42:04 +0530 | [diff] [blame] | 127 | config EXCLUDE_NATIVE_SD_INTERFACE |
128 | bool | ||||
129 | default n | ||||
130 | help | ||||
131 | If you set this option to n, will not use native SD controller. | ||||
132 | |||||
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 133 | config HEAP_SIZE |
134 | hex | ||||
135 | default 0x80000 | ||||
136 | |||||
137 | config IED_REGION_SIZE | ||||
138 | hex | ||||
139 | default 0x400000 | ||||
140 | |||||
Subrata Banik | e7ceae7 | 2017-03-08 17:59:40 +0530 | [diff] [blame] | 141 | config PCR_BASE_ADDRESS |
142 | hex | ||||
143 | default 0xfd000000 | ||||
144 | help | ||||
145 | This option allows you to select MMIO Base Address of sideband bus. | ||||
146 | |||||
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 147 | config SMM_RESERVED_SIZE |
148 | hex | ||||
149 | default 0x200000 | ||||
150 | |||||
151 | config SMM_TSEG_SIZE | ||||
152 | hex | ||||
153 | default 0x800000 | ||||
154 | |||||
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 155 | config VGA_BIOS_ID |
156 | string | ||||
157 | default "8086,0406" | ||||
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 158 | |
Teo Boon Tiong | 2fc06c8 | 2016-09-15 11:11:45 +0800 | [diff] [blame] | 159 | config SKYLAKE_SOC_PCH_H |
160 | bool | ||||
161 | default n | ||||
162 | help | ||||
163 | Choose this option if you have a PCH-H chipset. | ||||
164 | |||||
Aaron Durbin | ed8a723 | 2015-11-24 12:35:06 -0600 | [diff] [blame] | 165 | config NHLT_DMIC_2CH |
166 | bool | ||||
167 | default n | ||||
168 | help | ||||
169 | Include DSP firmware settings for 2 channel DMIC array. | ||||
170 | |||||
171 | config NHLT_DMIC_4CH | ||||
172 | bool | ||||
173 | default n | ||||
174 | help | ||||
175 | Include DSP firmware settings for 4 channel DMIC array. | ||||
176 | |||||
177 | config NHLT_NAU88L25 | ||||
178 | bool | ||||
179 | default n | ||||
180 | help | ||||
181 | Include DSP firmware settings for nau88l25 headset codec. | ||||
182 | |||||
183 | config NHLT_MAX98357 | ||||
184 | bool | ||||
185 | default n | ||||
186 | help | ||||
187 | Include DSP firmware settings for max98357 amplifier. | ||||
188 | |||||
Duncan Laurie | e6c8a38 | 2018-03-26 02:45:02 -0700 | [diff] [blame] | 189 | config NHLT_MAX98373 |
190 | bool | ||||
191 | default n | ||||
192 | help | ||||
193 | Include DSP firmware settings for max98373 amplifier. | ||||
194 | |||||
Aaron Durbin | ed8a723 | 2015-11-24 12:35:06 -0600 | [diff] [blame] | 195 | config NHLT_SSM4567 |
196 | bool | ||||
197 | default n | ||||
198 | help | ||||
199 | Include DSP firmware settings for ssm4567 smart amplifier. | ||||
200 | |||||
Duncan Laurie | 4a75a66 | 2017-03-02 10:13:51 -0800 | [diff] [blame] | 201 | config NHLT_RT5514 |
202 | bool | ||||
203 | default n | ||||
204 | help | ||||
205 | Include DSP firmware settings for rt5514 DSP. | ||||
206 | |||||
Rizwan Qureshi | 17335fa | 2017-01-14 06:08:21 +0530 | [diff] [blame] | 207 | config NHLT_RT5663 |
208 | bool | ||||
209 | default n | ||||
210 | help | ||||
211 | Include DSP firmware settings for rt5663 headset codec. | ||||
212 | |||||
213 | config NHLT_MAX98927 | ||||
214 | bool | ||||
215 | default n | ||||
216 | help | ||||
217 | Include DSP firmware settings for max98927 amplifier. | ||||
218 | |||||
Naveen Manohar | 83670c5 | 2017-11-04 02:55:09 +0530 | [diff] [blame] | 219 | config NHLT_DA7219 |
220 | bool | ||||
221 | default n | ||||
222 | help | ||||
223 | Include DSP firmware settings for DA7219 headset codec. | ||||
224 | |||||
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 225 | config FSP_HEADER_PATH |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 226 | # Use KabylakeFsp for both Skylake and Kabylake as it supports both. |
227 | # SkylakeFsp is FSP 1.1 and therefore incompatible. | ||||
Michael Niewöhner | 0f91f79 | 2019-10-05 19:47:47 +0200 | [diff] [blame] | 228 | default "3rdparty/fsp/KabylakeFspBinPkg/Include/" |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 229 | |
230 | config FSP_FD_PATH | ||||
Michael Niewöhner | 0f91f79 | 2019-10-05 19:47:47 +0200 | [diff] [blame] | 231 | default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 232 | |
Rizwan Qureshi | d8bb69a | 2016-11-08 21:01:09 +0530 | [diff] [blame] | 233 | config MAX_ROOT_PORTS |
234 | int | ||||
Michael Niewöhner | 0f91f79 | 2019-10-05 19:47:47 +0200 | [diff] [blame] | 235 | default 24 |
Rizwan Qureshi | d8bb69a | 2016-11-08 21:01:09 +0530 | [diff] [blame] | 236 | |
Jenny TC | 2864f85 | 2017-02-09 16:01:59 +0530 | [diff] [blame] | 237 | config NO_FADT_8042 |
238 | bool | ||||
239 | default n | ||||
240 | help | ||||
241 | Choose this option if you want to disable 8042 Keyboard | ||||
242 | |||||
Aaron Durbin | 551e4be | 2018-04-10 09:24:54 -0600 | [diff] [blame] | 243 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
Furquan Shaikh | 340908a | 2017-04-04 11:47:19 -0700 | [diff] [blame] | 244 | int |
245 | default 120 | ||||
246 | |||||
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 247 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
248 | int | ||||
Aaron Durbin | 551e4be | 2018-04-10 09:24:54 -0600 | [diff] [blame] | 249 | default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 250 | |
Furquan Shaikh | 05a6f29 | 2017-03-31 14:02:47 -0700 | [diff] [blame] | 251 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
252 | int | ||||
253 | default 2 | ||||
254 | |||||
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 255 | config SOC_INTEL_I2C_DEV_MAX |
256 | int | ||||
257 | default 6 | ||||
258 | |||||
Aamir Bohra | 1041d39 | 2017-06-02 11:56:14 +0530 | [diff] [blame] | 259 | config CPU_BCLK_MHZ |
260 | int | ||||
261 | default 100 | ||||
262 | |||||
Nico Huber | 9995418 | 2019-05-29 23:33:06 +0200 | [diff] [blame] | 263 | config CONSOLE_UART_BASE_ADDRESS |
264 | hex | ||||
265 | default 0xfe030000 | ||||
266 | depends on INTEL_LPSS_UART_FOR_CONSOLE | ||||
267 | |||||
Furquan Shaikh | 3406dd6 | 2017-08-04 15:58:26 -0700 | [diff] [blame] | 268 | # Clock divider parameters for 115200 baud rate |
269 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL | ||||
270 | hex | ||||
271 | default 0x30 | ||||
272 | |||||
273 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL | ||||
274 | hex | ||||
275 | default 0xc35 | ||||
276 | |||||
Furquan Shaikh | a3ad990 | 2018-03-21 10:45:08 -0700 | [diff] [blame] | 277 | config IFD_CHIPSET |
278 | string | ||||
279 | default "sklkbl" | ||||
280 | |||||
Patrick Rudolph | 5fffb5e | 2019-07-25 11:55:30 +0200 | [diff] [blame] | 281 | config INTEL_TXT_BIOSACM_ALIGNMENT |
282 | hex | ||||
283 | default 0x40000 # 256KB | ||||
284 | |||||
Wim Vervoorn | 2ab4f4b | 2019-10-23 10:22:06 +0200 | [diff] [blame] | 285 | config MAINBOARD_SUPPORTS_SKYLAKE_CPU |
286 | bool "Board can contain Skylake CPU" | ||||
287 | default y | ||||
288 | |||||
289 | if SKYLAKE_SOC_PCH_H | ||||
290 | |||||
291 | config MAINBOARD_SUPPORTS_KABYLAKE_CPU | ||||
292 | bool "Board can contain Kaby Lake CPU" | ||||
293 | default y if SOC_INTEL_KABYLAKE | ||||
294 | |||||
295 | endif | ||||
296 | |||||
297 | if !SKYLAKE_SOC_PCH_H | ||||
298 | |||||
299 | config MAINBOARD_SUPPORTS_KABYLAKE_DUAL | ||||
300 | bool "Board can contain Kaby Lake DUAL core" | ||||
301 | default y | ||||
302 | |||||
303 | config MAINBOARD_SUPPORTS_KABYLAKE_QUAD | ||||
304 | bool "Board can contain Kaby Lake QUAD core" | ||||
305 | default y | ||||
306 | |||||
307 | endif | ||||
308 | |||||
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 309 | endif |