Angel Pons | f4a9955 | 2020-04-02 20:12:40 +0200 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
| 3 | config SOUTHBRIDGE_INTEL_LYNXPOINT |
| 4 | bool |
Kyösti Mälkki | 81dc352 | 2023-04-08 09:43:56 +0300 | [diff] [blame] | 5 | select ACPI_COMMON_MADT_IOAPIC |
Kyösti Mälkki | 69a1396 | 2023-04-08 14:10:48 +0300 | [diff] [blame] | 6 | select ACPI_COMMON_MADT_LAPIC |
Aaron Durbin | da5f509 | 2016-07-13 23:23:16 -0500 | [diff] [blame] | 7 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Kyösti Mälkki | 661ad46 | 2020-12-29 06:26:21 +0200 | [diff] [blame] | 8 | select ACPI_SOC_NVS |
Felix Held | bc6a690 | 2023-11-09 14:08:53 +0100 | [diff] [blame^] | 9 | select AZALIA_HDA_CODEC_SUPPORT |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 10 | select SOUTHBRIDGE_INTEL_COMMON_SMBUS |
Angel Pons | 6428577 | 2020-06-01 20:06:03 +0200 | [diff] [blame] | 11 | select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS |
Arthur Heymans | 47a6603 | 2019-10-25 23:43:14 +0200 | [diff] [blame] | 12 | select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 13 | select SOUTHBRIDGE_INTEL_COMMON_FINALIZE |
Patrick Rudolph | a3caa2d | 2019-03-24 14:59:45 +0100 | [diff] [blame] | 14 | select SOUTHBRIDGE_INTEL_COMMON_PMCLIB |
Arthur Heymans | b8bda11 | 2019-06-04 13:57:47 +0200 | [diff] [blame] | 15 | select SOUTHBRIDGE_INTEL_COMMON_PMBASE |
Arthur Heymans | 074730c | 2019-06-04 14:05:53 +0200 | [diff] [blame] | 16 | select SOUTHBRIDGE_INTEL_COMMON_RTC |
Arthur Heymans | 23a6c79 | 2019-10-13 22:36:04 +0200 | [diff] [blame] | 17 | select SOUTHBRIDGE_INTEL_COMMON_RESET |
Tristan Corrick | 8a34795 | 2018-12-02 03:23:11 +1300 | [diff] [blame] | 18 | select HAVE_SMI_HANDLER |
Kyösti Mälkki | 0306b50 | 2013-08-13 09:10:31 +0300 | [diff] [blame] | 19 | select HAVE_USBDEBUG_OPTIONS |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 20 | select USE_WATCHDOG_ON_BOOT |
| 21 | select PCIEXP_ASPM |
| 22 | select PCIEXP_COMMON_CLOCK |
Stefan Tauner | ef8b957 | 2018-09-06 00:34:28 +0200 | [diff] [blame] | 23 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Angel Pons | 12d48cd | 2020-10-03 12:22:04 +0200 | [diff] [blame] | 24 | select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT |
Aaron Durbin | 16246ea | 2016-08-05 21:23:37 -0500 | [diff] [blame] | 25 | select RTC |
Patrick Rudolph | 273a8dc | 2016-02-06 18:07:59 +0100 | [diff] [blame] | 26 | select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP |
Tristan Corrick | f3127d4 | 2018-10-31 02:25:54 +1300 | [diff] [blame] | 27 | select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ |
Bill XIE | d533b16 | 2017-08-22 16:26:22 +0800 | [diff] [blame] | 28 | select HAVE_INTEL_CHIPSET_LOCKDOWN |
Nico Huber | 9faae2b | 2018-11-14 00:00:35 +0100 | [diff] [blame] | 29 | select HAVE_POWER_STATE_AFTER_FAILURE |
| 30 | select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE |
Elyes HAOUAS | 551a759 | 2019-05-01 16:56:36 +0200 | [diff] [blame] | 31 | select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG |
Arthur Heymans | 3457df1 | 2019-11-16 10:04:41 +0100 | [diff] [blame] | 32 | select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG |
Kyösti Mälkki | e8a3af1 | 2022-11-19 18:39:22 +0200 | [diff] [blame] | 33 | select TCO_SPACE_NOT_YET_SPLIT |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 34 | |
Elyes Haouas | ce61679 | 2023-08-04 18:07:27 +0200 | [diff] [blame] | 35 | if SOUTHBRIDGE_INTEL_LYNXPOINT |
| 36 | |
Duncan Laurie | fb9928f | 2012-12-17 11:11:26 -0800 | [diff] [blame] | 37 | config INTEL_LYNXPOINT_LP |
| 38 | bool |
| 39 | default n |
| 40 | help |
Angel Pons | 1708a2f | 2021-06-14 12:05:40 +0200 | [diff] [blame] | 41 | Set this option to y for LynxPoint LP (Haswell ULT). |
Duncan Laurie | fb9928f | 2012-12-17 11:11:26 -0800 | [diff] [blame] | 42 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 43 | config EHCI_BAR |
| 44 | hex |
Angel Pons | 6c42d14 | 2021-06-14 13:53:44 +0200 | [diff] [blame] | 45 | default 0xd8000000 if USE_BROADWELL_MRC |
Kyösti Mälkki | 0306b50 | 2013-08-13 09:10:31 +0300 | [diff] [blame] | 46 | default 0xe8000000 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 47 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 48 | config SERIRQ_CONTINUOUS_MODE |
| 49 | bool |
| 50 | default n |
| 51 | help |
| 52 | If you set this option to y, the serial IRQ machine will be |
| 53 | operated in continuous mode. |
| 54 | |
Angel Pons | 2d35cf8 | 2020-10-29 19:28:44 +0100 | [diff] [blame] | 55 | config HPET_MIN_TICKS |
Angel Pons | 2d35cf8 | 2020-10-29 19:28:44 +0100 | [diff] [blame] | 56 | default 0x80 |
| 57 | |
Duncan Laurie | 911cedf | 2013-07-30 16:05:55 -0700 | [diff] [blame] | 58 | config FINALIZE_USB_ROUTE_XHCI |
| 59 | bool "Route all ports to XHCI controller in finalize step" |
| 60 | default y |
| 61 | help |
| 62 | If you set this option to y, the USB ports will be routed |
| 63 | to the XHCI controller during the finalize SMM callback. |
| 64 | |
Matt DeVillier | 7f63353 | 2020-10-07 13:11:58 -0500 | [diff] [blame] | 65 | config PCIEXP_AER |
| 66 | bool |
| 67 | default y |
| 68 | |
Angel Pons | d4ba2b1 | 2021-10-12 21:01:13 +0200 | [diff] [blame] | 69 | config PCIEXP_CLK_PM |
| 70 | default y |
| 71 | |
| 72 | config PCIEXP_L1_SUB_STATE |
| 73 | default y |
| 74 | |
Angel Pons | aced1f0 | 2021-04-18 23:57:21 +0200 | [diff] [blame] | 75 | config SERIALIO_UART_CONSOLE |
| 76 | bool "Use SerialIO UART for console" |
| 77 | depends on INTEL_LYNXPOINT_LP |
| 78 | select DRIVERS_UART_8250MEM_32 |
| 79 | help |
| 80 | Selected by mainboards where SerialIO UARTs can be used to retrieve |
| 81 | coreboot logs. Boards also need to set UART_FOR_CONSOLE accordingly. |
| 82 | |
| 83 | config CONSOLE_UART_BASE_ADDRESS |
| 84 | default 0xd6000000 if SERIALIO_UART_CONSOLE |
| 85 | |
Matt DeVillier | 52c553e | 2022-12-21 14:47:37 -0600 | [diff] [blame] | 86 | config DISABLE_ME_PCI |
| 87 | bool "Disable Intel ME PCI interface (MEI1)" |
| 88 | default y |
| 89 | help |
| 90 | Disable and hide the ME PCI interface during finalize stage of boot. |
| 91 | This will prevent the OS (and userspace apps) from interacting with |
| 92 | the ME via the PCI interface after boot. |
| 93 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 94 | endif |