blob: dc25b850d881d6466b8559eb296e82cc5b3f5310 [file] [log] [blame]
Aaron Durbin76c37002012-10-30 09:03:43 -05001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2011 Google Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
Aaron Durbin76c37002012-10-30 09:03:43 -050015
16config SOUTHBRIDGE_INTEL_LYNXPOINT
17 bool
18
19if SOUTHBRIDGE_INTEL_LYNXPOINT
20
21config SOUTH_BRIDGE_OPTIONS # dummy
22 def_bool y
Aaron Durbinda5f5092016-07-13 23:23:16 -050023 select ACPI_INTEL_HARDWARE_SLEEP_VALUES
Kyösti Mälkki71216c92013-07-28 23:39:37 +030024 select SOUTHBRIDGE_INTEL_COMMON
Arthur Heymans16fe7902017-04-12 17:01:31 +020025 select SOUTHBRIDGE_INTEL_COMMON_SMBUS
Arthur Heymansbddef0d2017-09-25 12:21:07 +020026 select SOUTHBRIDGE_INTEL_COMMON_SPI
Aaron Durbin76c37002012-10-30 09:03:43 -050027 select IOAPIC
28 select HAVE_HARD_RESET
Kyösti Mälkki0306b502013-08-13 09:10:31 +030029 select HAVE_USBDEBUG_OPTIONS
Aaron Durbin76c37002012-10-30 09:03:43 -050030 select USE_WATCHDOG_ON_BOOT
31 select PCIEXP_ASPM
32 select PCIEXP_COMMON_CLOCK
Stefan Tauneref8b9572018-09-06 00:34:28 +020033 select INTEL_DESCRIPTOR_MODE_CAPABLE
Martin Roth3a543182015-09-28 15:27:24 -060034 select HAVE_SPI_CONSOLE_SUPPORT
Aaron Durbin16246ea2016-08-05 21:23:37 -050035 select RTC
Patrick Rudolph273a8dc2016-02-06 18:07:59 +010036 select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP
Bill XIEd533b162017-08-22 16:26:22 +080037 select HAVE_INTEL_CHIPSET_LOCKDOWN
Aaron Durbin76c37002012-10-30 09:03:43 -050038
Duncan Lauriefb9928f2012-12-17 11:11:26 -080039config INTEL_LYNXPOINT_LP
40 bool
41 default n
42 help
43 Set this option to y for Lynxpont LP (Haswell ULT).
44
Aaron Durbin76c37002012-10-30 09:03:43 -050045config EHCI_BAR
46 hex
Kyösti Mälkki0306b502013-08-13 09:10:31 +030047 default 0xe8000000
Aaron Durbin76c37002012-10-30 09:03:43 -050048
Aaron Durbin76c37002012-10-30 09:03:43 -050049config BOOTBLOCK_SOUTHBRIDGE_INIT
50 string
51 default "southbridge/intel/lynxpoint/bootblock.c"
52
53config SERIRQ_CONTINUOUS_MODE
54 bool
55 default n
56 help
57 If you set this option to y, the serial IRQ machine will be
58 operated in continuous mode.
59
Duncan Laurie3d299c42013-07-19 08:48:05 -070060config ME_MBP_CLEAR_LATE
61 bool "Defer wait for ME MBP Cleared"
62 default y
63 help
64 If you set this option to y, the Management Engine driver
65 will defer waiting for the MBP Cleared indicator until the
66 finalize step. This can speed up boot time if the ME takes
67 a long time to indicate this status.
68
Duncan Laurie911cedf2013-07-30 16:05:55 -070069config FINALIZE_USB_ROUTE_XHCI
70 bool "Route all ports to XHCI controller in finalize step"
71 default y
72 help
73 If you set this option to y, the USB ports will be routed
74 to the XHCI controller during the finalize SMM callback.
75
Duncan Laurie5a45b042013-08-22 09:56:42 -070076config LOCK_MANAGEMENT_ENGINE
Martin Roth59aa2b12015-06-20 16:17:12 -060077 bool
Duncan Laurie5a45b042013-08-22 09:56:42 -070078 default n
Duncan Laurie5a45b042013-08-22 09:56:42 -070079
Aaron Durbin76c37002012-10-30 09:03:43 -050080endif