sb/intel/common: Create a common PCH finalise implementation
The common finalise code is used by bd82x6x, Lynx Point, and Ibex Peak.
Lynx Point now benefits from being able to write-protect the flash chip.
For Lynx Point, writing the SPI OPMENU now happens in ramstage, as done
in bd82x6x.
Tested on an ASRock H81M-HDS (Lynx Point). When write-protection is
configured, flashrom reports all flash regions as read-only, and does
not manage to alter the contents of the flash chip.
Also tested on an ASUS P8H61-M LX (Cougar Point). Everything seems to
work as before.
Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/29977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index 5b06c4b..b331ba1 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -25,6 +25,7 @@
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI
select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
+ select SOUTHBRIDGE_INTEL_COMMON_FINALIZE
select IOAPIC
select HAVE_USBDEBUG_OPTIONS
select USE_WATCHDOG_ON_BOOT