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Angel Ponsf4a99552020-04-02 20:12:40 +02001## SPDX-License-Identifier: GPL-2.0-only
Aaron Durbin76c37002012-10-30 09:03:43 -05002
3config SOUTHBRIDGE_INTEL_LYNXPOINT
4 bool
5
6if SOUTHBRIDGE_INTEL_LYNXPOINT
7
Elyes HAOUAS00b5f532021-02-01 09:45:08 +01008config SOUTH_BRIDGE_OPTIONS
Aaron Durbin76c37002012-10-30 09:03:43 -05009 def_bool y
Aaron Durbinda5f5092016-07-13 23:23:16 -050010 select ACPI_INTEL_HARDWARE_SLEEP_VALUES
Kyösti Mälkki661ad462020-12-29 06:26:21 +020011 select ACPI_SOC_NVS
Angel Pons61dd8362020-12-05 18:02:32 +010012 select AZALIA_PLUGIN_SUPPORT
Arthur Heymans16fe7902017-04-12 17:01:31 +020013 select SOUTHBRIDGE_INTEL_COMMON_SMBUS
Angel Pons64285772020-06-01 20:06:03 +020014 select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
Arthur Heymans47a66032019-10-25 23:43:14 +020015 select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
Tristan Corrick167a5122018-10-31 02:28:32 +130016 select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
Tristan Corrick63626b12018-11-30 22:53:50 +130017 select SOUTHBRIDGE_INTEL_COMMON_FINALIZE
Patrick Rudolpha3caa2d2019-03-24 14:59:45 +010018 select SOUTHBRIDGE_INTEL_COMMON_PMCLIB
Arthur Heymansb8bda112019-06-04 13:57:47 +020019 select SOUTHBRIDGE_INTEL_COMMON_PMBASE
Arthur Heymans074730c2019-06-04 14:05:53 +020020 select SOUTHBRIDGE_INTEL_COMMON_RTC
Arthur Heymans23a6c792019-10-13 22:36:04 +020021 select SOUTHBRIDGE_INTEL_COMMON_RESET
Aaron Durbin76c37002012-10-30 09:03:43 -050022 select IOAPIC
Tristan Corrick8a347952018-12-02 03:23:11 +130023 select HAVE_SMI_HANDLER
Kyösti Mälkki0306b502013-08-13 09:10:31 +030024 select HAVE_USBDEBUG_OPTIONS
Aaron Durbin76c37002012-10-30 09:03:43 -050025 select USE_WATCHDOG_ON_BOOT
26 select PCIEXP_ASPM
27 select PCIEXP_COMMON_CLOCK
Stefan Tauneref8b9572018-09-06 00:34:28 +020028 select INTEL_DESCRIPTOR_MODE_CAPABLE
Angel Pons12d48cd2020-10-03 12:22:04 +020029 select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT
Aaron Durbin16246ea2016-08-05 21:23:37 -050030 select RTC
Patrick Rudolph273a8dc2016-02-06 18:07:59 +010031 select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP
Tristan Corrickf3127d42018-10-31 02:25:54 +130032 select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
Bill XIEd533b162017-08-22 16:26:22 +080033 select HAVE_INTEL_CHIPSET_LOCKDOWN
Nico Huber9faae2b2018-11-14 00:00:35 +010034 select HAVE_POWER_STATE_AFTER_FAILURE
35 select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
Elyes HAOUAS551a7592019-05-01 16:56:36 +020036 select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
Arthur Heymans3457df12019-11-16 10:04:41 +010037 select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
Aaron Durbin76c37002012-10-30 09:03:43 -050038
Duncan Lauriefb9928f2012-12-17 11:11:26 -080039config INTEL_LYNXPOINT_LP
40 bool
41 default n
42 help
43 Set this option to y for Lynxpont LP (Haswell ULT).
44
Aaron Durbin76c37002012-10-30 09:03:43 -050045config EHCI_BAR
46 hex
Kyösti Mälkki0306b502013-08-13 09:10:31 +030047 default 0xe8000000
Aaron Durbin76c37002012-10-30 09:03:43 -050048
Aaron Durbin76c37002012-10-30 09:03:43 -050049config SERIRQ_CONTINUOUS_MODE
50 bool
51 default n
52 help
53 If you set this option to y, the serial IRQ machine will be
54 operated in continuous mode.
55
Angel Pons2d35cf82020-10-29 19:28:44 +010056config HPET_MIN_TICKS
57 hex
58 default 0x80
59
Duncan Laurie911cedf2013-07-30 16:05:55 -070060config FINALIZE_USB_ROUTE_XHCI
61 bool "Route all ports to XHCI controller in finalize step"
62 default y
63 help
64 If you set this option to y, the USB ports will be routed
65 to the XHCI controller during the finalize SMM callback.
66
Matt DeVillier7f633532020-10-07 13:11:58 -050067config PCIEXP_AER
68 bool
69 default y
70
Angel Ponsaced1f02021-04-18 23:57:21 +020071config SERIALIO_UART_CONSOLE
72 bool "Use SerialIO UART for console"
73 depends on INTEL_LYNXPOINT_LP
74 select DRIVERS_UART_8250MEM_32
75 help
76 Selected by mainboards where SerialIO UARTs can be used to retrieve
77 coreboot logs. Boards also need to set UART_FOR_CONSOLE accordingly.
78
79config CONSOLE_UART_BASE_ADDRESS
80 default 0xd6000000 if SERIALIO_UART_CONSOLE
81
Aaron Durbin76c37002012-10-30 09:03:43 -050082endif