blob: 431744f08c5cddf33bea53f77757b04298123085 [file] [log] [blame]
Aaron Durbin76c37002012-10-30 09:03:43 -05001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2011 Google Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
Aaron Durbin76c37002012-10-30 09:03:43 -050015
16config SOUTHBRIDGE_INTEL_LYNXPOINT
17 bool
18
19if SOUTHBRIDGE_INTEL_LYNXPOINT
20
21config SOUTH_BRIDGE_OPTIONS # dummy
22 def_bool y
Aaron Durbinda5f5092016-07-13 23:23:16 -050023 select ACPI_INTEL_HARDWARE_SLEEP_VALUES
Kyösti Mälkki71216c92013-07-28 23:39:37 +030024 select SOUTHBRIDGE_INTEL_COMMON
Arthur Heymans16fe7902017-04-12 17:01:31 +020025 select SOUTHBRIDGE_INTEL_COMMON_SMBUS
Arthur Heymansbddef0d2017-09-25 12:21:07 +020026 select SOUTHBRIDGE_INTEL_COMMON_SPI
Tristan Corrick167a5122018-10-31 02:28:32 +130027 select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
Tristan Corrick63626b12018-11-30 22:53:50 +130028 select SOUTHBRIDGE_INTEL_COMMON_FINALIZE
Patrick Rudolpha3caa2d2019-03-24 14:59:45 +010029 select SOUTHBRIDGE_INTEL_COMMON_PMCLIB
Aaron Durbin76c37002012-10-30 09:03:43 -050030 select IOAPIC
Tristan Corrick8a347952018-12-02 03:23:11 +130031 select HAVE_SMI_HANDLER
Kyösti Mälkki0306b502013-08-13 09:10:31 +030032 select HAVE_USBDEBUG_OPTIONS
Aaron Durbin76c37002012-10-30 09:03:43 -050033 select USE_WATCHDOG_ON_BOOT
34 select PCIEXP_ASPM
35 select PCIEXP_COMMON_CLOCK
Stefan Tauneref8b9572018-09-06 00:34:28 +020036 select INTEL_DESCRIPTOR_MODE_CAPABLE
Martin Roth3a543182015-09-28 15:27:24 -060037 select HAVE_SPI_CONSOLE_SUPPORT
Aaron Durbin16246ea2016-08-05 21:23:37 -050038 select RTC
Patrick Rudolph273a8dc2016-02-06 18:07:59 +010039 select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP
Tristan Corrickf3127d42018-10-31 02:25:54 +130040 select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
Bill XIEd533b162017-08-22 16:26:22 +080041 select HAVE_INTEL_CHIPSET_LOCKDOWN
Tristan Corrickb2632ce2018-10-31 02:28:13 +130042 select COMMON_FADT
Nico Huber9faae2b2018-11-14 00:00:35 +010043 select HAVE_POWER_STATE_AFTER_FAILURE
44 select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
Aaron Durbin76c37002012-10-30 09:03:43 -050045
Duncan Lauriefb9928f2012-12-17 11:11:26 -080046config INTEL_LYNXPOINT_LP
47 bool
48 default n
49 help
50 Set this option to y for Lynxpont LP (Haswell ULT).
51
Aaron Durbin76c37002012-10-30 09:03:43 -050052config EHCI_BAR
53 hex
Kyösti Mälkki0306b502013-08-13 09:10:31 +030054 default 0xe8000000
Aaron Durbin76c37002012-10-30 09:03:43 -050055
Aaron Durbin76c37002012-10-30 09:03:43 -050056config BOOTBLOCK_SOUTHBRIDGE_INIT
57 string
58 default "southbridge/intel/lynxpoint/bootblock.c"
59
60config SERIRQ_CONTINUOUS_MODE
61 bool
62 default n
63 help
64 If you set this option to y, the serial IRQ machine will be
65 operated in continuous mode.
66
Duncan Laurie3d299c42013-07-19 08:48:05 -070067config ME_MBP_CLEAR_LATE
68 bool "Defer wait for ME MBP Cleared"
69 default y
70 help
71 If you set this option to y, the Management Engine driver
72 will defer waiting for the MBP Cleared indicator until the
73 finalize step. This can speed up boot time if the ME takes
74 a long time to indicate this status.
75
Duncan Laurie911cedf2013-07-30 16:05:55 -070076config FINALIZE_USB_ROUTE_XHCI
77 bool "Route all ports to XHCI controller in finalize step"
78 default y
79 help
80 If you set this option to y, the USB ports will be routed
81 to the XHCI controller during the finalize SMM callback.
82
Aaron Durbin76c37002012-10-30 09:03:43 -050083endif