| Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame^] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2011 Google Inc. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
| 15 | ## You should have received a copy of the GNU General Public License |
| 16 | ## along with this program; if not, write to the Free Software |
| 17 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | ## |
| 19 | |
| 20 | config SOUTHBRIDGE_INTEL_LYNXPOINT |
| 21 | bool |
| 22 | |
| 23 | if SOUTHBRIDGE_INTEL_LYNXPOINT |
| 24 | |
| 25 | config SOUTH_BRIDGE_OPTIONS # dummy |
| 26 | def_bool y |
| 27 | select IOAPIC |
| 28 | select HAVE_HARD_RESET |
| 29 | select HAVE_USBDEBUG |
| 30 | select USE_WATCHDOG_ON_BOOT |
| 31 | select PCIEXP_ASPM |
| 32 | select PCIEXP_COMMON_CLOCK |
| 33 | select SPI_FLASH |
| 34 | |
| 35 | config EHCI_BAR |
| 36 | hex |
| 37 | default 0xfef00000 |
| 38 | |
| 39 | config EHCI_DEBUG_OFFSET |
| 40 | hex |
| 41 | default 0xa0 |
| 42 | |
| 43 | config BOOTBLOCK_SOUTHBRIDGE_INIT |
| 44 | string |
| 45 | default "southbridge/intel/lynxpoint/bootblock.c" |
| 46 | |
| 47 | config SERIRQ_CONTINUOUS_MODE |
| 48 | bool |
| 49 | default n |
| 50 | help |
| 51 | If you set this option to y, the serial IRQ machine will be |
| 52 | operated in continuous mode. |
| 53 | |
| 54 | endif |