blob: 646d480dd8a8c50dc152f47b02211338c20a33b5 [file] [log] [blame]
Aaron Durbin76c37002012-10-30 09:03:43 -05001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2011 Google Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
Aaron Durbin76c37002012-10-30 09:03:43 -050015
16config SOUTHBRIDGE_INTEL_LYNXPOINT
17 bool
18
19if SOUTHBRIDGE_INTEL_LYNXPOINT
20
21config SOUTH_BRIDGE_OPTIONS # dummy
22 def_bool y
Aaron Durbinda5f5092016-07-13 23:23:16 -050023 select ACPI_INTEL_HARDWARE_SLEEP_VALUES
Kyösti Mälkki71216c92013-07-28 23:39:37 +030024 select SOUTHBRIDGE_INTEL_COMMON
Arthur Heymans16fe7902017-04-12 17:01:31 +020025 select SOUTHBRIDGE_INTEL_COMMON_SMBUS
Aaron Durbin76c37002012-10-30 09:03:43 -050026 select IOAPIC
27 select HAVE_HARD_RESET
Kyösti Mälkki0306b502013-08-13 09:10:31 +030028 select HAVE_USBDEBUG_OPTIONS
Aaron Durbin76c37002012-10-30 09:03:43 -050029 select USE_WATCHDOG_ON_BOOT
30 select PCIEXP_ASPM
31 select PCIEXP_COMMON_CLOCK
32 select SPI_FLASH
Martin Roth59aa2b12015-06-20 16:17:12 -060033 select HAVE_INTEL_FIRMWARE
Martin Roth3a543182015-09-28 15:27:24 -060034 select HAVE_SPI_CONSOLE_SUPPORT
Aaron Durbin16246ea2016-08-05 21:23:37 -050035 select RTC
Patrick Rudolph273a8dc2016-02-06 18:07:59 +010036 select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP
Bill XIEd533b162017-08-22 16:26:22 +080037 select HAVE_INTEL_CHIPSET_LOCKDOWN
Aaron Durbin76c37002012-10-30 09:03:43 -050038
Duncan Lauriefb9928f2012-12-17 11:11:26 -080039config INTEL_LYNXPOINT_LP
40 bool
41 default n
42 help
43 Set this option to y for Lynxpont LP (Haswell ULT).
44
Aaron Durbin76c37002012-10-30 09:03:43 -050045config EHCI_BAR
46 hex
Kyösti Mälkki0306b502013-08-13 09:10:31 +030047 default 0xe8000000
Aaron Durbin76c37002012-10-30 09:03:43 -050048
Aaron Durbin76c37002012-10-30 09:03:43 -050049config BOOTBLOCK_SOUTHBRIDGE_INIT
50 string
51 default "southbridge/intel/lynxpoint/bootblock.c"
52
53config SERIRQ_CONTINUOUS_MODE
54 bool
55 default n
56 help
57 If you set this option to y, the serial IRQ machine will be
58 operated in continuous mode.
59
Paul Menzel5218e612014-06-16 09:28:36 +020060config HAVE_IFD_BIN
61 bool
62 default y
63
64config BUILD_WITH_FAKE_IFD
Martin Roth59aa2b12015-06-20 16:17:12 -060065 bool
Paul Menzel5218e612014-06-16 09:28:36 +020066 default y if !HAVE_IFD_BIN
Paul Menzel5218e612014-06-16 09:28:36 +020067
68config IFD_BIN_PATH
Martin Roth59aa2b12015-06-20 16:17:12 -060069 string
Paul Menzel5218e612014-06-16 09:28:36 +020070 depends on !BUILD_WITH_FAKE_IFD
Patrick Georgi26e24cc2015-05-05 22:27:25 +020071 default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
Paul Menzel5218e612014-06-16 09:28:36 +020072
Paul Menzel0089c242014-06-16 14:59:44 +020073config HAVE_ME_BIN
Martin Roth59aa2b12015-06-20 16:17:12 -060074 bool
Paul Menzel0089c242014-06-16 14:59:44 +020075 default y
Paul Menzel0089c242014-06-16 14:59:44 +020076
Patrick Georgi3cc151e2013-06-13 15:07:02 +020077config ME_BIN_PATH
Martin Roth59aa2b12015-06-20 16:17:12 -060078 string
Paul Menzel0089c242014-06-16 14:59:44 +020079 depends on HAVE_ME_BIN
Patrick Georgi26e24cc2015-05-05 22:27:25 +020080 default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
Patrick Georgi3cc151e2013-06-13 15:07:02 +020081
Duncan Laurie3d299c42013-07-19 08:48:05 -070082config ME_MBP_CLEAR_LATE
83 bool "Defer wait for ME MBP Cleared"
84 default y
85 help
86 If you set this option to y, the Management Engine driver
87 will defer waiting for the MBP Cleared indicator until the
88 finalize step. This can speed up boot time if the ME takes
89 a long time to indicate this status.
90
Duncan Laurie911cedf2013-07-30 16:05:55 -070091config FINALIZE_USB_ROUTE_XHCI
92 bool "Route all ports to XHCI controller in finalize step"
93 default y
94 help
95 If you set this option to y, the USB ports will be routed
96 to the XHCI controller during the finalize SMM callback.
97
Duncan Laurie5a45b042013-08-22 09:56:42 -070098config LOCK_MANAGEMENT_ENGINE
Martin Roth59aa2b12015-06-20 16:17:12 -060099 bool
Duncan Laurie5a45b042013-08-22 09:56:42 -0700100 default n
Duncan Laurie5a45b042013-08-22 09:56:42 -0700101
Aaron Durbin76c37002012-10-30 09:03:43 -0500102endif