blob: 31a7db3fa2a16926060099ff96b3d807b693c740 [file] [log] [blame]
Aaron Durbin76c37002012-10-30 09:03:43 -05001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2011 Google Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
Aaron Durbin76c37002012-10-30 09:03:43 -050015
16config SOUTHBRIDGE_INTEL_LYNXPOINT
17 bool
18
19if SOUTHBRIDGE_INTEL_LYNXPOINT
20
21config SOUTH_BRIDGE_OPTIONS # dummy
22 def_bool y
Aaron Durbinda5f5092016-07-13 23:23:16 -050023 select ACPI_INTEL_HARDWARE_SLEEP_VALUES
Kyösti Mälkki71216c92013-07-28 23:39:37 +030024 select SOUTHBRIDGE_INTEL_COMMON
Aaron Durbin76c37002012-10-30 09:03:43 -050025 select IOAPIC
26 select HAVE_HARD_RESET
Kyösti Mälkki0306b502013-08-13 09:10:31 +030027 select HAVE_USBDEBUG_OPTIONS
Aaron Durbin76c37002012-10-30 09:03:43 -050028 select USE_WATCHDOG_ON_BOOT
29 select PCIEXP_ASPM
30 select PCIEXP_COMMON_CLOCK
31 select SPI_FLASH
Martin Roth59aa2b12015-06-20 16:17:12 -060032 select HAVE_INTEL_FIRMWARE
Martin Roth3a543182015-09-28 15:27:24 -060033 select HAVE_SPI_CONSOLE_SUPPORT
Aaron Durbin16246ea2016-08-05 21:23:37 -050034 select RTC
Patrick Rudolph273a8dc2016-02-06 18:07:59 +010035 select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP
Aaron Durbin76c37002012-10-30 09:03:43 -050036
Duncan Lauriefb9928f2012-12-17 11:11:26 -080037config INTEL_LYNXPOINT_LP
38 bool
39 default n
40 help
41 Set this option to y for Lynxpont LP (Haswell ULT).
42
Aaron Durbin76c37002012-10-30 09:03:43 -050043config EHCI_BAR
44 hex
Kyösti Mälkki0306b502013-08-13 09:10:31 +030045 default 0xe8000000
Aaron Durbin76c37002012-10-30 09:03:43 -050046
Aaron Durbin76c37002012-10-30 09:03:43 -050047config BOOTBLOCK_SOUTHBRIDGE_INIT
48 string
49 default "southbridge/intel/lynxpoint/bootblock.c"
50
51config SERIRQ_CONTINUOUS_MODE
52 bool
53 default n
54 help
55 If you set this option to y, the serial IRQ machine will be
56 operated in continuous mode.
57
Paul Menzel5218e612014-06-16 09:28:36 +020058config HAVE_IFD_BIN
59 bool
60 default y
61
62config BUILD_WITH_FAKE_IFD
Martin Roth59aa2b12015-06-20 16:17:12 -060063 bool
Paul Menzel5218e612014-06-16 09:28:36 +020064 default y if !HAVE_IFD_BIN
Paul Menzel5218e612014-06-16 09:28:36 +020065
66config IFD_BIN_PATH
Martin Roth59aa2b12015-06-20 16:17:12 -060067 string
Paul Menzel5218e612014-06-16 09:28:36 +020068 depends on !BUILD_WITH_FAKE_IFD
Patrick Georgi26e24cc2015-05-05 22:27:25 +020069 default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
Paul Menzel5218e612014-06-16 09:28:36 +020070
Paul Menzel0089c242014-06-16 14:59:44 +020071config HAVE_ME_BIN
Martin Roth59aa2b12015-06-20 16:17:12 -060072 bool
Paul Menzel0089c242014-06-16 14:59:44 +020073 default y
Paul Menzel0089c242014-06-16 14:59:44 +020074
Patrick Georgi3cc151e2013-06-13 15:07:02 +020075config ME_BIN_PATH
Martin Roth59aa2b12015-06-20 16:17:12 -060076 string
Paul Menzel0089c242014-06-16 14:59:44 +020077 depends on HAVE_ME_BIN
Patrick Georgi26e24cc2015-05-05 22:27:25 +020078 default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
Patrick Georgi3cc151e2013-06-13 15:07:02 +020079
Duncan Laurie3d299c42013-07-19 08:48:05 -070080config ME_MBP_CLEAR_LATE
81 bool "Defer wait for ME MBP Cleared"
82 default y
83 help
84 If you set this option to y, the Management Engine driver
85 will defer waiting for the MBP Cleared indicator until the
86 finalize step. This can speed up boot time if the ME takes
87 a long time to indicate this status.
88
Duncan Laurie911cedf2013-07-30 16:05:55 -070089config FINALIZE_USB_ROUTE_XHCI
90 bool "Route all ports to XHCI controller in finalize step"
91 default y
92 help
93 If you set this option to y, the USB ports will be routed
94 to the XHCI controller during the finalize SMM callback.
95
Duncan Laurie5a45b042013-08-22 09:56:42 -070096config LOCK_MANAGEMENT_ENGINE
Martin Roth59aa2b12015-06-20 16:17:12 -060097 bool
Duncan Laurie5a45b042013-08-22 09:56:42 -070098 default n
Duncan Laurie5a45b042013-08-22 09:56:42 -070099
Prabal Saha0f2025d2016-06-18 20:47:21 -0700100config LYNXPOINT_POWER_OPTIMIZER
101 bool "Enable Power Optimizer"
102 default y if CHROMEOS
103 help
104 Enable the power optimizer for the High Speed I/O
105 Power Control (HSIOPC). This can break graphics
106 under Windows, but can improve battery life under
107 'mostly idle' conditions.
108
Aaron Durbin76c37002012-10-30 09:03:43 -0500109endif