Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2011 Google Inc. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 15 | |
| 16 | config SOUTHBRIDGE_INTEL_LYNXPOINT |
| 17 | bool |
| 18 | |
| 19 | if SOUTHBRIDGE_INTEL_LYNXPOINT |
| 20 | |
| 21 | config SOUTH_BRIDGE_OPTIONS # dummy |
| 22 | def_bool y |
Aaron Durbin | da5f509 | 2016-07-13 23:23:16 -0500 | [diff] [blame] | 23 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Kyösti Mälkki | 71216c9 | 2013-07-28 23:39:37 +0300 | [diff] [blame] | 24 | select SOUTHBRIDGE_INTEL_COMMON |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 25 | select IOAPIC |
| 26 | select HAVE_HARD_RESET |
Kyösti Mälkki | 0306b50 | 2013-08-13 09:10:31 +0300 | [diff] [blame] | 27 | select HAVE_USBDEBUG_OPTIONS |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 28 | select USE_WATCHDOG_ON_BOOT |
| 29 | select PCIEXP_ASPM |
| 30 | select PCIEXP_COMMON_CLOCK |
| 31 | select SPI_FLASH |
Martin Roth | 59aa2b1 | 2015-06-20 16:17:12 -0600 | [diff] [blame] | 32 | select HAVE_INTEL_FIRMWARE |
Martin Roth | 3a54318 | 2015-09-28 15:27:24 -0600 | [diff] [blame] | 33 | select HAVE_SPI_CONSOLE_SUPPORT |
Aaron Durbin | 16246ea | 2016-08-05 21:23:37 -0500 | [diff] [blame^] | 34 | select RTC |
Patrick Rudolph | 273a8dc | 2016-02-06 18:07:59 +0100 | [diff] [blame] | 35 | select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 36 | |
Duncan Laurie | fb9928f | 2012-12-17 11:11:26 -0800 | [diff] [blame] | 37 | config INTEL_LYNXPOINT_LP |
| 38 | bool |
| 39 | default n |
| 40 | help |
| 41 | Set this option to y for Lynxpont LP (Haswell ULT). |
| 42 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 43 | config EHCI_BAR |
| 44 | hex |
Kyösti Mälkki | 0306b50 | 2013-08-13 09:10:31 +0300 | [diff] [blame] | 45 | default 0xe8000000 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 46 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 47 | config BOOTBLOCK_SOUTHBRIDGE_INIT |
| 48 | string |
| 49 | default "southbridge/intel/lynxpoint/bootblock.c" |
| 50 | |
| 51 | config SERIRQ_CONTINUOUS_MODE |
| 52 | bool |
| 53 | default n |
| 54 | help |
| 55 | If you set this option to y, the serial IRQ machine will be |
| 56 | operated in continuous mode. |
| 57 | |
Paul Menzel | 5218e61 | 2014-06-16 09:28:36 +0200 | [diff] [blame] | 58 | config HAVE_IFD_BIN |
| 59 | bool |
| 60 | default y |
| 61 | |
| 62 | config BUILD_WITH_FAKE_IFD |
Martin Roth | 59aa2b1 | 2015-06-20 16:17:12 -0600 | [diff] [blame] | 63 | bool |
Paul Menzel | 5218e61 | 2014-06-16 09:28:36 +0200 | [diff] [blame] | 64 | default y if !HAVE_IFD_BIN |
Paul Menzel | 5218e61 | 2014-06-16 09:28:36 +0200 | [diff] [blame] | 65 | |
| 66 | config IFD_BIN_PATH |
Martin Roth | 59aa2b1 | 2015-06-20 16:17:12 -0600 | [diff] [blame] | 67 | string |
Paul Menzel | 5218e61 | 2014-06-16 09:28:36 +0200 | [diff] [blame] | 68 | depends on !BUILD_WITH_FAKE_IFD |
Patrick Georgi | 26e24cc | 2015-05-05 22:27:25 +0200 | [diff] [blame] | 69 | default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" |
Paul Menzel | 5218e61 | 2014-06-16 09:28:36 +0200 | [diff] [blame] | 70 | |
Paul Menzel | 0089c24 | 2014-06-16 14:59:44 +0200 | [diff] [blame] | 71 | config HAVE_ME_BIN |
Martin Roth | 59aa2b1 | 2015-06-20 16:17:12 -0600 | [diff] [blame] | 72 | bool |
Paul Menzel | 0089c24 | 2014-06-16 14:59:44 +0200 | [diff] [blame] | 73 | default y |
Paul Menzel | 0089c24 | 2014-06-16 14:59:44 +0200 | [diff] [blame] | 74 | |
Patrick Georgi | 3cc151e | 2013-06-13 15:07:02 +0200 | [diff] [blame] | 75 | config ME_BIN_PATH |
Martin Roth | 59aa2b1 | 2015-06-20 16:17:12 -0600 | [diff] [blame] | 76 | string |
Paul Menzel | 0089c24 | 2014-06-16 14:59:44 +0200 | [diff] [blame] | 77 | depends on HAVE_ME_BIN |
Patrick Georgi | 26e24cc | 2015-05-05 22:27:25 +0200 | [diff] [blame] | 78 | default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" |
Patrick Georgi | 3cc151e | 2013-06-13 15:07:02 +0200 | [diff] [blame] | 79 | |
Duncan Laurie | 3d299c4 | 2013-07-19 08:48:05 -0700 | [diff] [blame] | 80 | config ME_MBP_CLEAR_LATE |
| 81 | bool "Defer wait for ME MBP Cleared" |
| 82 | default y |
| 83 | help |
| 84 | If you set this option to y, the Management Engine driver |
| 85 | will defer waiting for the MBP Cleared indicator until the |
| 86 | finalize step. This can speed up boot time if the ME takes |
| 87 | a long time to indicate this status. |
| 88 | |
Duncan Laurie | 911cedf | 2013-07-30 16:05:55 -0700 | [diff] [blame] | 89 | config FINALIZE_USB_ROUTE_XHCI |
| 90 | bool "Route all ports to XHCI controller in finalize step" |
| 91 | default y |
| 92 | help |
| 93 | If you set this option to y, the USB ports will be routed |
| 94 | to the XHCI controller during the finalize SMM callback. |
| 95 | |
Duncan Laurie | 5a45b04 | 2013-08-22 09:56:42 -0700 | [diff] [blame] | 96 | config LOCK_MANAGEMENT_ENGINE |
Martin Roth | 59aa2b1 | 2015-06-20 16:17:12 -0600 | [diff] [blame] | 97 | bool |
Duncan Laurie | 5a45b04 | 2013-08-22 09:56:42 -0700 | [diff] [blame] | 98 | default n |
Duncan Laurie | 5a45b04 | 2013-08-22 09:56:42 -0700 | [diff] [blame] | 99 | |
Prabal Saha | 0f2025d | 2016-06-18 20:47:21 -0700 | [diff] [blame] | 100 | config LYNXPOINT_POWER_OPTIMIZER |
| 101 | bool "Enable Power Optimizer" |
| 102 | default y if CHROMEOS |
| 103 | help |
| 104 | Enable the power optimizer for the High Speed I/O |
| 105 | Power Control (HSIOPC). This can break graphics |
| 106 | under Windows, but can improve battery life under |
| 107 | 'mostly idle' conditions. |
| 108 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 109 | endif |