Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2007 AMD |
| 5 | * Written by Yinghai Lu <yinghailu@amd.com> for AMD. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 16 | */ |
| 17 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 18 | #include <stdint.h> |
Patrick Georgi | 12aba82 | 2009-04-30 07:07:22 +0000 | [diff] [blame] | 19 | #include <string.h> |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 20 | #include <device/pci_def.h> |
| 21 | #include <device/pci_ids.h> |
| 22 | #include <arch/io.h> |
| 23 | #include <device/pnp_def.h> |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 24 | #include <cpu/x86/lapic.h> |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 25 | #include <pc80/mc146818rtc.h> |
Patrick Georgi | 12584e2 | 2010-05-08 09:14:51 +0000 | [diff] [blame] | 26 | #include <console/console.h> |
Uwe Hermann | 6dc92f0 | 2010-11-21 11:36:03 +0000 | [diff] [blame] | 27 | #include <spd.h> |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 28 | #include <cpu/amd/model_fxx_rev.h> |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 29 | #include "southbridge/nvidia/mcp55/early_smbus.c" |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 30 | #include <northbridge/amd/amdk8/raminit.h> |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 31 | #include "lib/delay.c" |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 32 | #include <cpu/x86/lapic.h> |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 33 | #include "northbridge/amd/amdk8/reset_test.c" |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 34 | #include <superio/ite/common/ite.h> |
Edward O'Callaghan | 5c41ee6 | 2014-04-23 01:43:38 +1000 | [diff] [blame] | 35 | #include <superio/ite/it8716f/it8716f.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 36 | #include <cpu/x86/bist.h> |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 37 | #include "northbridge/amd/amdk8/debug.c" |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 38 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 39 | #include "southbridge/nvidia/mcp55/early_ctrl.c" |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 40 | |
| 41 | #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) |
Edward O'Callaghan | 5c41ee6 | 2014-04-23 01:43:38 +1000 | [diff] [blame] | 42 | #define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 43 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 44 | static void memreset(int controllers, const struct mem_controller *ctrl) { } |
| 45 | static void activate_spd_rom(const struct mem_controller *ctrl) { } |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 46 | |
| 47 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 48 | { |
| 49 | return smbus_read_byte(device, address); |
| 50 | } |
| 51 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 52 | #define MCP55_MB_SETUP \ |
Torsten Duwe | e7537f1 | 2007-10-31 00:49:38 +0000 | [diff] [blame] | 53 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x68,/* GPIO38 PCI_REQ3 */ \ |
| 54 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \ |
| 55 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x68,/* GPIO40 PCI_GNT2 */ \ |
| 56 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x68,/* GPIO41 PCI_REQ2 */ \ |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 57 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ |
| 58 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ |
| 59 | |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 60 | #include <southbridge/nvidia/mcp55/early_setup_ss.h> |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 61 | #include "southbridge/nvidia/mcp55/early_setup_car.c" |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 62 | #include <northbridge/amd/amdk8/f.h> |
Stefan Reinauer | d55e26f | 2010-04-25 13:54:30 +0000 | [diff] [blame] | 63 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
| 64 | #include "northbridge/amd/amdk8/coherent_ht.c" |
| 65 | #include "northbridge/amd/amdk8/raminit_f.c" |
| 66 | #include "lib/generic_sdram.c" |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 67 | #include "resourcemap.c" |
Stefan Reinauer | d55e26f | 2010-04-25 13:54:30 +0000 | [diff] [blame] | 68 | #include "cpu/amd/dualcore/dualcore.c" |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 69 | #include "cpu/amd/model_fxx/init_cpus.c" |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 70 | #include "cpu/amd/model_fxx/fidvid.c" |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 71 | #include "northbridge/amd/amdk8/early_ht.c" |
| 72 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 73 | static void sio_setup(void) |
| 74 | { |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 75 | uint32_t dword; |
| 76 | uint8_t byte; |
| 77 | |
| 78 | byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 79 | byte |= 0x20; |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 80 | pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 81 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 82 | dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); |
| 83 | dword |= (1<<0); |
| 84 | pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 85 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 86 | dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); |
| 87 | dword |= (1<<16); |
| 88 | pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); |
| 89 | } |
| 90 | |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 91 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 92 | { |
| 93 | static const uint16_t spd_addr [] = { |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 94 | // Node 0 |
| 95 | DIMM0, DIMM2, 0, 0, |
| 96 | DIMM1, DIMM3, 0, 0, |
| 97 | // Node 1 |
| 98 | DIMM4, DIMM6, 0, 0, |
| 99 | DIMM5, DIMM7, 0, 0, |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 100 | }; |
| 101 | |
Patrick Georgi | bbc880e | 2012-11-20 18:20:56 +0100 | [diff] [blame] | 102 | struct sys_info *sysinfo = &sysinfo_car; |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 103 | int needs_reset = 0; |
| 104 | unsigned bsp_apicid = 0; |
| 105 | |
Patrick Georgi | 2bd9100 | 2010-03-18 16:46:50 +0000 | [diff] [blame] | 106 | if (!cpu_init_detectedx && boot_cpu()) { |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 107 | /* Nothing special needs to be done to find bus 0 */ |
| 108 | /* Allow the HT devices to be found */ |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 109 | enumerate_ht_chain(); |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 110 | sio_setup(); |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 111 | } |
| 112 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 113 | if (bist == 0) |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 114 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 115 | |
Edward O'Callaghan | 5c41ee6 | 2014-04-23 01:43:38 +1000 | [diff] [blame] | 116 | #if 0 |
| 117 | uint8_t tmp = 0; |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 118 | pnp_enter_ext_func_mode(SERIAL_DEV); |
Carl-Daniel Hailfinger | e13abe5 | 2007-11-14 17:57:04 +0000 | [diff] [blame] | 119 | /* The following line will set CLKIN to 24 MHz, external */ |
| 120 | pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11); |
Carl-Daniel Hailfinger | 34153ac | 2007-11-14 15:09:30 +0000 | [diff] [blame] | 121 | tmp = pnp_read_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP); |
| 122 | /* Is serial flash enabled? Then enable writing to serial flash. */ |
| 123 | if (tmp & 0x0e) { |
| 124 | pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP, tmp | 0x10); |
| 125 | pnp_set_logical_device(GPIO_DEV); |
| 126 | /* Set Serial Flash interface to 0x0820 */ |
| 127 | pnp_write_config(GPIO_DEV, 0x64, 0x08); |
| 128 | pnp_write_config(GPIO_DEV, 0x65, 0x20); |
Carl-Daniel Hailfinger | 34153ac | 2007-11-14 15:09:30 +0000 | [diff] [blame] | 129 | } |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 130 | it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 131 | pnp_exit_ext_func_mode(SERIAL_DEV); |
Edward O'Callaghan | 5c41ee6 | 2014-04-23 01:43:38 +1000 | [diff] [blame] | 132 | #endif |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 133 | ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); |
| 134 | ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 135 | |
| 136 | setup_mb_resource_map(); |
| 137 | |
Stefan Reinauer | 42fa7fe | 2011-04-20 20:54:07 +0000 | [diff] [blame] | 138 | console_init(); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 139 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 140 | /* Halt if there was a built in self test failure */ |
| 141 | report_bist_failure(bist); |
| 142 | |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 143 | printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n", sysinfo, sysinfo+1); |
| 144 | printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 145 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 146 | set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 147 | setup_coherent_ht_domain(); // routing table and start other core0 |
| 148 | |
| 149 | wait_all_core0_started(); |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 150 | #if CONFIG_LOGICAL_CPUS |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 151 | // It is said that we should start core1 after all core0 launched |
| 152 | /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, |
| 153 | * So here need to make sure last core0 is started, esp for two way system, |
| 154 | * (there may be apic id conflicts in that case) |
| 155 | */ |
| 156 | start_other_cores(); |
| 157 | wait_all_other_cores_started(bsp_apicid); |
| 158 | #endif |
| 159 | |
| 160 | /* it will set up chains and store link pair for optimization later */ |
| 161 | ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn |
| 162 | |
Patrick Georgi | 76e8152 | 2010-11-16 21:25:29 +0000 | [diff] [blame] | 163 | #if CONFIG_SET_FIDVID |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 164 | { |
| 165 | msr_t msr; |
| 166 | msr=rdmsr(0xc0010042); |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 167 | printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 168 | } |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 169 | enable_fid_change(); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 170 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 171 | init_fidvid_bsp(bsp_apicid); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 172 | // show final fid and vid |
| 173 | { |
| 174 | msr_t msr; |
| 175 | msr=rdmsr(0xc0010042); |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 176 | printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 177 | } |
| 178 | #endif |
| 179 | |
Paul Menzel | 4549e5a | 2014-02-02 22:05:48 +0100 | [diff] [blame] | 180 | init_timer(); // Need to use TMICT to synchronize FID/VID |
Stefan Reinauer | bcb8c97 | 2010-04-25 18:06:32 +0000 | [diff] [blame] | 181 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 182 | needs_reset |= optimize_link_coherent_ht(); |
| 183 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 184 | needs_reset |= mcp55_early_setup_x(); |
| 185 | |
| 186 | // fidvid change will issue one LDTSTOP and the HT change will be effective too |
| 187 | if (needs_reset) { |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 188 | printk(BIOS_INFO, "ht reset -\n"); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 189 | soft_reset(); |
| 190 | } |
| 191 | allow_all_aps_stop(bsp_apicid); |
| 192 | |
| 193 | //It's the time to set ctrl in sysinfo now; |
| 194 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 195 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 196 | enable_smbus(); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 197 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 198 | /* all ap stopped? */ |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 199 | |
| 200 | sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |
| 201 | |
| 202 | post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 203 | } |